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1. 发明申请

WO2017048474A1 LOW-POWER DOUBLE ERROR CORRECTING-TRIPLE ERROR DETECTING (DEB-TED) DECODER 审中-公开
标题翻译：低功率双重错误校正三位差错检测（DEB-TED）解码器
公开(公告)号：WO2017048474A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/048604
申请日：2016-08-25
申请人： QUALCOMM INCORPORATED , INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
发明人： JUNG, Seong-Ook , CHOI, Sara , SONG, Byung Kyu , NA, Taehui , KIM, Jisu , KIM, Jung Pill , KIM, Sungryul , KIM, Taehyun , KANG, Seung Hyuk
IPC分类号： H03M13/15 , G06F11/10 , H03M13/00
CPC分类号： H03M13/616 , G06F11/10 , G06F11/1012 , H03M13/152 , H03M13/1575 , H03M13/617 , H03M13/6502
摘要： Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.
摘要翻译：错误检测和校正解码装置根据数据输入是否包含单位错误或多位错误，执行单纠错双重错误检测（SEC-DED）或双纠错三重错误检测（DEC-TED），以在单位错误的情况下降低功耗和延迟，并在多位错误的情况下提供强大的纠错。

2. 发明申请

WO2016171862A1 SYSTEM, APPARATUS, AND METHOD FOR A SENSE CIRCUIT 审中-公开
标题翻译：用于感知电路的系统，装置和方法
公开(公告)号：WO2016171862A1
公开(公告)日：2016-10-27
申请号：PCT/US2016/025170
申请日：2016-03-31
申请人： QUALCOMM INCORPORATED , INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
发明人： JUNG, Seong-Ook , NA, Taehui , KIM, Jisu , KIM, Jung Pill , KANG, Seung Hyuk
IPC分类号： G11C7/06 , G11C13/00
CPC分类号： G11C7/08 , G11C7/067 , G11C7/10 , G11C7/1051 , G11C7/22 , G11C11/1673 , G11C13/004 , G11C16/26
摘要： A read circuit for a memory cell may include an integrated logic circuit for sensing a current change. The integrated logic sensing circuit may be an offset cancelling single ended integrated logic sensing circuit. The circuit may include an offset canceling single ended sensing circuit coupled to a supply voltage, an offset canceling single ended sense amplifier circuit having a sense amplifier input coupled to the offset canceling single ended sensing circuit and a sense amplifier output, and a cell array coupled to a sensing circuit output and a ground.
摘要翻译：用于存储单元的读取电路可以包括用于感测电流变化的集成逻辑电路。集成逻辑感测电路可以是偏移消除单端集成逻辑感测电路。电路可以包括耦合到电源电压的偏移消除单端感测电路，具有耦合到偏移消除单端感测电路的读出放大器输入和读出放大器输出的偏移消除单端读出放大器电路，以及耦合到到感测电路输出和地。

3. 发明申请

WO2016048887A2 CONSTANT SENSING CURRENT FOR READING RESISTIVE MEMORY 审中-公开
标题翻译：用于读取电阻记忆体的恒定感应电流
公开(公告)号：WO2016048887A2
公开(公告)日：2016-03-31
申请号：PCT/US2015/051208
申请日：2015-09-21
申请人： QUALCOMM INCORPORATED , INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
发明人： JUNG, Seong-Ook , CHOI, Sara , KIM, Jisu , NA, Taehui , KIM, Jung Pill , KANG, Seung Hyuk
IPC分类号： G11C7/08
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/08 , G11C7/14 , G11C13/004 , G11C2013/0045 , G11C2013/0054
摘要： Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.
摘要翻译：系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。通过将从恒定电流反射的感测电流通过电阻性存储元件，基于产生的负载电压产生数据电压。产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。

4. 发明申请

WO2016048739A1 LATCH OFFSET CANCELATION SENSE AMPLIFIER 审中-公开
标题翻译： LATCH偏移取消感应放大器
公开(公告)号：WO2016048739A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/050361
申请日：2015-09-16
申请人： QUALCOMM INCORPORATED , INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
发明人： JUNG, Seong-Ook , NA, Taehui , SONG, Byungkyu , KIM, Jung Pill , KANG, Seung Hyuk
IPC分类号： G11C11/16 , G11C7/06 , G11C7/08 , G11C7/12
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/165 , G11C11/1653 , G11C11/1655 , G11C11/1675 , G11C2207/002
摘要： Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the preamplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.
摘要翻译：系统和方法涉及使用多阶段配置的电路的磁阻随机存取存储器（MRAM）位单元的操作。在感测电路阶段，电路被配置为确定位单元两端的数据电压与参考电压之间的第一差分电压。在预放大阶段，电路被配置为对第一差分电压进行预放大，以产生预放大的差分电压，其不会由于工艺变化而产生偏移电压。在读出放大器相位中，电路被配置为在锁存器中放大预放大的差分电压。预放大的差分电压的产生可消除锁存器中可能出现的偏移电压。在写入阶段，电路还被配置为将写入数据值写入MRAM位单元。

5. 发明申请

WO2022072056A1 CIRCUITS EMPLOYING A BACK SIDE-FRONT SIDE CONNECTION STRUCTURE FOR COUPLING BACK SIDE ROUTING TO FRONT SIDE ROUTING, AND RELATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS AND METHODS 审中-公开
公开(公告)号：WO2022072056A1
公开(公告)日：2022-04-07
申请号：PCT/US2021/044191
申请日：2021-08-02
申请人： QUALCOMM INCORPORATED
发明人： LIM, Hyeokjin , SONG, Stanley Seungchul , VANG, Foua , KANG, Seung Hyuk
IPC分类号： H01L23/48 , H01L23/528 , H01L27/105
摘要： Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

6. 发明申请

WO2018038849A1 HIGH SPEED, LOW POWER SPIN-ORBIT TORQUE (SOT) ASSISTED SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY (STT-MRAM) BIT CELL ARRAY 审中-公开
标题翻译：高速，低功率旋转轨道转矩（SOT）辅助自旋转换转矩磁随机存取存储器（STT-MRAM）BIT CELL ARRAY
公开(公告)号：WO2018038849A1
公开(公告)日：2018-03-01
申请号：PCT/US2017/043691
申请日：2017-07-25
申请人： QUALCOMM INCORPORATED
发明人： KAN, Jimmy Jianan , PARK, Chando , WANG, Peiyuan , KIM, Sungryul , KANG, Seung Hyuk
IPC分类号： G11C11/16
摘要： A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells includes a perpendicular magnetic tunnel junction (pMTJ) -a magnetic tunnel junction with perpendicular anisotropy- including a reference layer, a barrier layer supporting the reference layer, and a free layer supporting the barrier layer. A spin-hall conductive material layer supports the free layer. A driver is operable to set a state of at least one of the plurality of bit cells, the driver being configured to simultaneously drive a current along the spin-Hall conductive material to generate via a Spin Hall effect a Spin Orbit Transfer -SOT- current flowing through the pMTJ and drive a further current through the pMTJ and a portion of the spin- hall conductive material layer, the further current generating with the reference layer a Spin-transfer-torque -STT- current through the pMTJ.
摘要翻译：描述了包括几个位单元的磁性随机存取存储器（MRAM）阵列。每个位单元包括垂直磁隧道结（pMTJ） - 具有垂直各向异性的磁隧道结 - 包括参考层，支撑参考层的阻挡层和支撑阻挡层的自由层。自旋层导电材料层支撑自由层。驱动器可操作以设置所述多个位单元中的至少一个的状态，所述驱动器被配置为沿着自旋霍尔导电材料同时驱动电流以经由自旋霍尔效应产生自旋轨道传输-SOT-电流流过pMTJ并驱动另一电流通过pMTJ和自旋霍尔导电材料层的一部分，进一步的电流与参考层一起产生通过pMTJ的自旋转移 - 转矩 - 电流 - 电流。

7. 发明申请

WO2016048681A1 LOGIC HIGH-K/METAL GATE 1T-1C RRAM MTP/OTP DEVICES 审中-公开
标题翻译： LOGIC高K /金属门1T-1C RRAM MTP / OTP器件
公开(公告)号：WO2016048681A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/049569
申请日：2015-09-11
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , PERRY JR., Daniel Wayne , KANG, Seung Hyuk
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： H01L27/2418 , G11C13/0007 , G11C13/0069 , G11C17/165 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/16
摘要： Methods and apparatuses, wherein the method includes providing a logic device. The method substantially surrounds a metal gate with a transition metal oxide on at least one side, wherein the transition metal oxide is comprised of hafnium oxalate and silicon dioxide. The method provides a bottom electrode (BE), wherein the BE is comprised of at least one of silicon or tungsten.
摘要翻译：方法和装置，其中所述方法包括提供逻辑装置。该方法基本上围绕在至少一侧上具有过渡金属氧化物的金属栅极，其中过渡金属氧化物由草酸铪和二氧化硅组成。该方法提供底电极（BE），其中BE由硅或钨中的至少一种构成。

8. 发明申请

WO2015148059A1 METHOD FOR FABRICATING A MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：制造磁性隧道结的方法
公开(公告)号：WO2015148059A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/018274
申请日：2015-03-02
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , LEE, Kangho , CHEN, Wei-Chuan , LU, Yu , PARK, Chando , KANG, Seung Hyuk
IPC分类号： H01L43/12
CPC分类号： H01L43/02 , G11C11/161 , H01L27/222 , H01L27/224 , H01L43/08 , H01L43/12
摘要： An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.
摘要翻译：提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。在一个实例中，提供了一种用于制造磁性隧道结（MTJ）的方法。该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

9. 发明申请

WO2015066529A1 METHOD AND APPARATUS FOR NON-VOLATILE RAM ERROR RE-MAPPING 审中-公开
标题翻译：非易失性RAM错误重新映射的方法和装置
公开(公告)号：WO2015066529A1
公开(公告)日：2015-05-07
申请号：PCT/US2014/063532
申请日：2014-10-31
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , KIM, Jung Pill , KANG, Seung Hyuk , KIM, Taehyun
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/1008 , G06F11/076 , G06F11/0766 , G06F11/1048 , G06F11/1068 , G06F12/0246 , G06F2212/7201 , G06F2212/7204 , G06F2212/7209
摘要： A memory module comprising a non-volatile cell array and a re-mapper. A page map table is stored in the non-volatile cell array, and includes mappings of old page addresses to new page addresses. The re-mapper is configured to direct memory operations referencing an old page address to the new page address that the old page address is mapped to. The mappings are created when a memory cell is determined to be in a failure state.
摘要翻译：一种包括非易失性单元阵列和重新映射器的存储器模块。页面映射表存储在非易失性单元阵列中，并且包括旧页地址到新页地址的映射。重映射器被配置为将引用旧页地址的内存操作定向到旧页地址被映射到的新页地址。当确定存储器单元处于故障状态时，创建映射。

10. 发明申请

WO2017034755A1 MAGNETIC FIELD ENHANCING BACKING PLATE FOR MRAM WAFER TESTING 审中-公开
标题翻译：用于MRAM波形测试的磁场增强背板
公开(公告)号：WO2017034755A1
公开(公告)日：2017-03-02
申请号：PCT/US2016/044593
申请日：2016-07-28
申请人： QUALCOMM INCORPORATED
发明人： KAN, Jimmy , GOTTWALD, Matthias Georg , PARK, Chando , KANG, Seung Hyuk
IPC分类号： G11C29/56 , G11C29/00 , G01R31/319
CPC分类号： G01R33/1207 , G11C11/16 , G11C29/006 , G11C29/04 , G11C29/56016 , G11C2029/1206 , G11C2029/5002 , G11C2029/5602
摘要： A method and apparatus for testing a magnetic memory device is provided. The method begins when a magnetic field enhancing backing plate is installed in the test fixture. The magnetic field enhancing backing plate may be installed in the wafer chuck of a wafer testing probe station. The magnetic memory device is installed in the test fixture and a magnetic field is applied to the magnetic memory device. The magnetic field may be applied in-plane or perpendicular to the magnetic memory device. The performance of the magnetic memory device may be determined based on the magnetic field applied to the device. The apparatus includes a magnetic field enhancing backing plate adapted to fit a test fixture, possibly in the wafer chuck. The magnetic field enhancing backing plate is fabricated of high permeability magnetic materials, such as low carbon steel, with a thickness based on the magnetic field used in testing.
摘要翻译：提供一种用于测试磁存储器件的方法和装置。当将磁场增强背板安装在测试夹具中时，该方法开始。磁场增强背板可以安装在晶片测试探针台的晶片卡盘中。磁存储器件安装在测试夹具中，磁场被施加到磁存储器件。磁场可以面向或垂直于磁存储器件施加。磁存储器件的性能可以基于施加到器件的磁场来确定。该装置包括适于装配测试夹具（可能在晶片卡盘中）的磁场增强背板。磁场增强背板由高磁导率磁性材料（如低碳钢）制成，厚度基于测试中使用的磁场。

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