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1. 发明申请

WO2013049763A1 METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL 审中-公开
标题翻译：减少多端口SRAM存储单元泄漏功率的方法和装置
公开(公告)号：WO2013049763A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058178
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
发明人： PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
IPC分类号： G11C11/413
CPC分类号： G11C11/413 , G11C5/148
摘要： Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.
摘要翻译：包括诸如8T SRAM单元的存储单元的存储器阵列中的减小泄漏电流和功耗的系统和方法。存储器阵列包括用于在睡眠模式或存储器单元组的非活动状态期间以降低功率状态动态地将一组存储器单元置于存储器阵列中的逻辑，从而有效地消除泄漏部分。存储器阵列还包括用于在对所选择的存储器单元进行读取或写入访问操作期间动态地启用所选存储器单元组的逻辑，其中相应的读取或写入位线在相应的后部或写入操作之前和之后被预充电。

2. 发明申请

WO2013040066A1 ADAPTIVE READ WORDLINE VOLTAGE BOOSTING APPARATUS AND METHOD FOR MULTI-PORT SRAM 审中-公开
标题翻译：适用于多端口SRAM的WORDLINE电压升压装置和方法
公开(公告)号：WO2013040066A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054907
申请日：2012-09-12
申请人： QUALCOMM INCORPORATED , GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
发明人： GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
IPC分类号： G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C11/418
摘要： Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) (104) in response to process-voltage-temperature variations when needed. Embodiments include a critical path (114) that simulates a typical memory cell (104) and read-out circuit (102) in the SRAM. Applying a trigger signal to a word-line input port (123) of the critical path, and comparing the output (125) of the critical path to a reference-latch signal (127), provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.
摘要翻译：本发明的实施例涉及用于在需要时响应于过程电压 - 温度变化自适应地将SRAM的电源电压升高到SRAM（静态随机存取存储器）（104）的系统和方法。实施例包括模拟SRAM中的典型存储单元（104）和读出电路（102）的关键路径（114）。将触发信号施加到关键路径的字线输入端口（123），并将关键路径的输出（125）与参考锁存信号（127）进行比较，提供何时升压电源电压的指示到SRAM的读出电路。

3. 发明申请

WO2008064172A2 CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：内容可寻址内存
公开(公告)号：WO2008064172A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/085129
申请日：2007-11-19
申请人： QUALCOMM Incorporated , CHAI, Chiaming , HOFF, David, Paul , MARTZLOFF, Jason, Philip , PHAN, Michael, Thaithanh , VARMA, Manju, Rathna
发明人： CHAI, Chiaming , HOFF, David, Paul , MARTZLOFF, Jason, Philip , PHAN, Michael, Thaithanh , VARMA, Manju, Rathna
IPC分类号： H01L21/8239 , H01L27/02 , H01L27/105 , G11C15/04
CPC分类号： H01L27/105 , G11C11/412 , G11C15/00 , G11C15/04 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/1052
摘要： A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.
摘要翻译：公开了内容可寻址存储器（CAM）。 CAM具有第一和第二CAM单元，其中每个相邻的CAM单元相对于其邻居旋转180°，这提供了具有整体匹配的CAM阵列单元和RAM阵列单元行高度的紧凑的物理布置。此外，交错集合方案可以应用于CAM单元，以提供比较信号的降低的路由以及降低的寄生电容。

4. 发明申请

WO2007051204A1 CIRCUIT AND METHOD FOR SUBDIVIDING A CAMRAM BANK BY CONTROLLING A VIRTUAL GROUND 审中-公开
标题翻译：通过控制虚拟地面来分散CAMRAM银行的电路和方法
公开(公告)号：WO2007051204A1
公开(公告)日：2007-05-03
申请号：PCT/US2006/060370
申请日：2006-10-30
申请人： QUALCOMM INCORPORATED , PHAN, Michael, ThaiThanh , CHAI, Chiaming , BRIDGES, Jeffrey, Todd , FISCHER, Jeffrey, Herbert
发明人： PHAN, Michael, ThaiThanh , CHAI, Chiaming , BRIDGES, Jeffrey, Todd , FISCHER, Jeffrey, Herbert
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G11C8/12 , G11C15/04
摘要： A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.
摘要翻译： CAM组在功能上划分为两个或更多个子行，不复制CAM驱动电路，禁止该组中的所有匹配线放电电路，并且选择性地使得放电电路在包含子行的条目中使能。至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。可以从地址位解码的控制信号被分配给切换电路以定义CAM子库。

5. 发明申请

WO2013040065A1 IMPROVING SRAM CELL WRITABILITY 审中-公开
标题翻译：改善SRAM单元的可写性
公开(公告)号：WO2013040065A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054906
申请日：2012-09-12
申请人： QUALCOMM Incorporated , GARG, Manish , PHAN, Michael ThaiThanh
发明人： GARG, Manish , PHAN, Michael ThaiThanh
IPC分类号： G11C7/04 , G11C8/16 , G11C11/413 , G11C11/417 , G11C11/418 , G11C29/02 , G11C29/24
CPC分类号： G11C7/04 , G11C8/16 , G11C11/413 , G11C11/417 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/24
摘要： Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value (114) corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated (110). This bias voltage value is applied to word lines of SRAM cells in a model SRAM array (130). A first delay (164) for a trigger signal (124) rippled through the model SRAM array is detected and compared to a reference delay (122). A write assist indication (162) is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.
摘要翻译：用于检测和改善静态随机存取存储器（SRAM）单元的可写性的系统和方法。产生对应于指示包括SRAM单元的外部SRAM阵列的单元写入故障状态的处理，电压或温度操作条件的操作条件的偏置电压值（110）（110）。该偏置电压值被施加到模型SRAM阵列中的SRAM单元的字线（130）。检测波形通过模型SRAM阵列的触发信号（124）的第一延迟（164）并将其与参考延迟（122）进行比较。如果第一延迟大于或等于参考延迟，则产生写辅助指示（162）。基于写入辅助指示，向SRAM单元提供写入辅助。

6. 发明申请

WO2011116316A2 METHOD AND APPARATUS FOR SUPPRESSING BITLINE COUPLING THROUGH MILLER CAPACITANCE TO A SENSE AMPLIFIER INTERSTITIAL NODE 审中-公开
标题翻译：抑制通过MILLER电容耦合到感测放大器间隙节点的方法和装置
公开(公告)号：WO2011116316A2
公开(公告)日：2011-09-22
申请号：PCT/US2011029046
申请日：2011-03-18
申请人： QUALCOMM INC , PHAN MICHAEL THAITHANH , CHAI CHIAMING , GARG MANISH
发明人： PHAN MICHAEL THAITHANH , CHAI CHIAMING , GARG MANISH
IPC分类号： G11C7/06
CPC分类号： G11C7/02 , G11C7/065
摘要： A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.
摘要翻译：实现读出放大器电路以抑制米勒效应电容耦合。放大器电路包括具有第一输入，第一输出空隙节点，第二输入，第二输出空隙节点，用于启用或禁用差分放大器的第三输入以及具有均衡器电路的差分放大器电路，所述均衡器电路耦合在第一输出插页式节点和第二个输出插页式节点。该放大器电路还包括具有耦合到第一输出间隙节点的第一锁存器输入，耦合到第二输出间隙节点的第二锁存器输入，第一锁存器输出和第二锁存器输出的交叉耦合锁存器电路，其中在第一第一锁存器输出和第二锁存器输出被预充电时，差分放大器电路被禁止，并且均衡器电路被启用以抑制感测放大器输入端上的米勒效应电容耦合。

7. 发明申请

WO2008064172A3 CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：内容可寻址内存
公开(公告)号：WO2008064172A3
公开(公告)日：2009-01-08
申请号：PCT/US2007085129
申请日：2007-11-19
申请人： QUALCOMM INC , CHAI CHIAMING , HOFF DAVID PAUL , MARTZLOFF JASON PHILIP , PHAN MICHAEL THAITHANH , VARMA MANJU RATHNA
发明人： CHAI CHIAMING , HOFF DAVID PAUL , MARTZLOFF JASON PHILIP , PHAN MICHAEL THAITHANH , VARMA MANJU RATHNA
IPC分类号： H01L21/8239 , G11C15/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L27/105
CPC分类号： H01L27/105 , G11C11/412 , G11C15/00 , G11C15/04 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/1052
摘要： A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells (710, 720, 730, 740) in which each adjacent CAM cell is rotated 180 relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance. The first and second CAM cells may be vertically stacked.
摘要翻译：公开了内容可寻址存储器（CAM）。 CAM具有第一和第二CAM单元（710,720,730,740），其中每个相邻的CAM单元相对于其邻居旋转180°，这提供了具有整体匹配的CAM阵列单元和RAM阵列单元行高度的紧凑的物理布置。此外，交错集合方案可以应用于CAM单元，以提供比较信号的降低的路由以及降低的寄生电容。第一和第二CAM单元可以垂直堆叠。

8. 发明申请

WO2013040061A1 APPARATUS FOR SELECTIVE WORD-LINE BOOST ON A MEMORY CELL 审中-公开
标题翻译：在存储单元上选择性的字线升压的装置
公开(公告)号：WO2013040061A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054902
申请日：2012-09-12
申请人： QUALCOMM Incorporated , GARG, Manish , PHAN, Michael ThaiThanh
发明人： GARG, Manish , PHAN, Michael ThaiThanh
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , G11C8/16 , G11C8/08
CPC分类号： G11C8/08 , G11C5/063 , G11C7/08 , G11C8/12 , G11C8/16 , G11C11/4085 , G11C11/412 , G11C11/418 , G11C11/419
摘要： Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.
摘要翻译：用于选择性地提高存储单元阵列中的字线（WL）电压的系统和方法。该方法依赖于几个实施例来最小化与WL升压方案相关联的能量成本。一个实施例产生瞬态升压而不是提供直流升压。瞬态升压生成可以以循环为基础进行控制，并且可以在不访问阵列时禁用。另一个实施例允许系统在WL驱动器附近本地产生瞬态电压升高，并且仅在需要时在周期期间产生。本地化的升压电压降低了需要升压到更高电压的负载电容。另一个实施例有效地将瞬态升压分配给WL驱动器。

9. 发明申请

WO2011116316A3 METHOD AND APPARATUS FOR SUPPRESSING BITLINE COUPLING THROUGH MILLER CAPACITANCE TO A SENSE AMPLIFIER INTERSTITIAL NODE 审中-公开
公开(公告)号：WO2011116316A3
公开(公告)日：2011-09-22
申请号：PCT/US2011/029046
申请日：2011-03-18
申请人： QUALCOMM INCORPORATED , PHAN, Michael ThaiThanh , CHAI, Chiaming , GARG, Manish
发明人： PHAN, Michael ThaiThanh , CHAI, Chiaming , GARG, Manish
IPC分类号： G11C7/06
摘要： A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

10. 发明申请

WO2008019274A3 METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：用于降低内容可寻址存储器中的功耗的方法和设备
公开(公告)号：WO2008019274A3
公开(公告)日：2008-04-10
申请号：PCT/US2007074999
申请日：2007-08-01
申请人： QUALCOMM INC , CHAI CHIAMING , FISCHER JEFFREY HERBERT , PHAN MICHAEL THAITHANH
发明人： CHAI CHIAMING , FISCHER JEFFREY HERBERT , PHAN MICHAEL THAITHANH
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit comprises a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.
摘要翻译：降低多级分层内容可寻址存储器（CAM）电路的功耗，同时不会对性能产生负面影响。根据多级分级CAM电路的一个实施例，CAM电路包括多个较低级匹配线，多个较高级匹配线和匹配线恢复电路。较低级匹配线被配置为在预评估期间恢复到预评估状态。较高级匹配线被配置为在评估时段期间捕获一个或多个较低级匹配线的各组的评估状态并且在预评估时段期间恢复到预评估状态。匹配线恢复电路被配置为响应于对应的使能信息例如指示匹配线搜索结果是否将被利用的一个或多个比特而防止至少一个较低级匹配线被恢复到预评估状态。

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