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1. 发明申请

WO2006096139A1 AN AUTHORING TOOL AND METHOD FOR CREATING AN ELECTRONIC DOCUMENT 审中-公开
标题翻译：用于创建电子文档的作者工具和方法
公开(公告)号：WO2006096139A1
公开(公告)日：2006-09-14
申请号：PCT/SG2006/000052
申请日：2006-03-10
申请人： NATIONAL UNIVERSITY OF SINGAPORE , GE, Shuzhi , CHEN, Xiangdong , HAN, Xiaoyan
发明人： GE, Shuzhi , CHEN, Xiangdong , HAN, Xiaoyan
IPC分类号： G06F17/21 , G06F17/30
CPC分类号： G06F17/248
摘要： An authoring tool for creating an electronic document, a method for creating the electronic document, a data storage medium for instructing a computer to execute the method for creating the electronic document and a data storage medium for instructing a computer to display the electronic document. The authoring tool comprises: a template module for selecting a template for the electronic document, the template comprising one or more display pages; a content management module for arranging one or more media files on each display page with selected interrelationships between the media files; a generating module for creating an electronic page file for each display page, wherein the media files are embedded in the respective electronic page files based on the selected interrelationships and in a manner such that each electronic page file includes interrelationship data defining the interrelationships of the embedded media files in said each electronic page file with other media files in said each electronic page file and with other media files in other electronic page files of the electronic document; and a binding module for electronically binding the respective electronic page files so as to create the electronic document.
摘要翻译：用于创建电子文档的创作工具，用于创建电子文档的方法，用于指示计算机执行创建电子文档的方法的数据存储介质和用于指示计算机显示电子文档的数据存储介质。创作工具包括：用于选择电子文档的模板的模板模块，模板包括一个或多个显示页面; 内容管理模块，用于在每个显示页面上布置一个或多个媒体文件，其中媒体文件之间具有选定的相互关系; 用于为每个显示页面创建电子页面文件的生成模块，其中基于所选择的相互关系将媒体文件嵌入在相应的电子页面文件中，并且以这样的方式使得每个电子页面文件包括定义嵌入的相互关系的相互关系数据所述每个电子页面文件中的媒体文件与所述每个电子页面文件中的其他媒体文件以及电子文档的其他电子页面文件中的其他媒体文件; 以及用于电子地绑定各个电子页面文件以便创建电子文档的装订模块。

2. 发明申请

WO2007090856A1 CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS, AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：具有混合信道方位的CMOS器件及其制造方法
公开(公告)号：WO2007090856A1
公开(公告)日：2007-08-16
申请号：PCT/EP2007/051189
申请日：2007-02-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHEN, Xiangdong , DYER, Thomas, Walter , TOOMEY, James, Joseph , YANG, Haining
发明人： CHEN, Xiangdong , DYER, Thomas, Walter , TOOMEY, James, Joseph , YANG, Haining
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a semiconductor substrate (12) comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces (25) oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces (35) oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底（12），其中第一器件区域包括具有沿第一组等效晶面取向的内表面（25）的第一凹槽，并且其中第二器件区域包括具有沿着第二不同组的等效晶面取向的内表面（35）的第二凹部。可以使用这种半导体衬底形成半导体器件结构。具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿第一凹槽的内表面延伸的沟道。至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。

3. 发明申请

WO2017147895A1 LOW-AREA LOW CLOCK-POWER FLIP-FLOP 审中-公开
标题翻译：低面积低功耗FLIP-FLOP
公开(公告)号：WO2017147895A1
公开(公告)日：2017-09-08
申请号：PCT/CN2016/075596
申请日：2016-03-04
申请人： QUALCOMM INCORPORATED , RASOULI, Seid Hadi , KANG, Hananel , CAI, Yanfei , CHEN, Xiangdong , BOYNAPALLI, Venugopal
发明人： RASOULI, Seid Hadi , KANG, Hananel , CAI, Yanfei , CHEN, Xiangdong , BOYNAPALLI, Venugopal
IPC分类号： H03K3/356 , H03K3/012 , H03K3/3562
CPC分类号： H03K3/012 , H03K3/35625
摘要： In one example, an apparatus may be a flip-flop that includes a slave latch and a master latch. The master latch includes a first logic element in the master latch. The first logic element includes a first transistor. The first transistor is shared by a second logic element in one of the master latch or the slave latch. The first transistor provides a clocking signal input to the first logic element and the second logic element.
摘要翻译：在一个示例中，装置可以是包括从锁存器和主锁存器的触发器。主锁存器包括主锁存器中的第一逻辑元件。第一逻辑元件包括第一晶体管。第一晶体管由主锁存器或从锁存器中的一个中的第二逻辑元件共享。第一晶体管向第一逻辑元件和第二逻辑元件提供时钟信号输入。

4. 发明申请

WO2011056391A2 HIGH-DRIVE CURRENT MOSFET 审中-公开
标题翻译：高驱动电流MOSFET
公开(公告)号：WO2011056391A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/052989
申请日：2010-10-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PARK, Jae-eun , WANG, Xinlin , CHEN, Xiangdong
发明人： PARK, Jae-eun , WANG, Xinlin , CHEN, Xiangdong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device 100 having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure 15 on a first portion of the substrate 5 having a well 35 of a first conductivity. A source region 20 of a second conductivity and drain region 25 of the second conductivity is formed within the well 35 of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region 30 of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件100的方法。在一个实施例中，该方法包括在具有第一导电性的阱35的衬底5的第一部分上形成栅极结构15。第二导电性的源极区域20和第二导电性的漏极区域25在衬底的与存在栅极结构的衬底的第一部分相邻的部分中的第一导电性的阱35内形成。第二导电性的掺杂区域30形成在漏极区域内以在半导体器件的漏极侧提供集成双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极第二导电类型的区域和发射极由存在于漏极区域中的第二导电类型的掺杂区域提供。还提供了由上述方法形成的半导体器件。

5. 发明申请

WO2008000556A1 IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：改进的具有应力通道区域的CMOS器件及其制造方法
公开(公告)号：WO2008000556A1
公开(公告)日：2008-01-03
申请号：PCT/EP2007/054932
申请日：2007-05-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHEN, Xiangdong , DYER, Thomas , SETTLEMEYER, Kenneth , YANG, Haining
发明人： CHEN, Xiangdong , DYER, Thomas , SETTLEMEYER, Kenneth , YANG, Haining
IPC分类号： H01L21/8238 , H01L21/336 , H01L29/78 , H01L29/04 , H01L29/10 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide- semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

6. 发明申请

WO2006078740A2 STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETS 审中-公开
标题翻译：在CMOSFET中优化应变的结构和方法
公开(公告)号：WO2006078740A2
公开(公告)日：2006-07-27
申请号：PCT/US2006001768
申请日：2006-01-19
申请人： IBM , CHEN XIANGDONG , YANG HAINING S
发明人： CHEN XIANGDONG , YANG HAINING S
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823842 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.
摘要翻译：公开了包括PMOSFET和NMOSFETS的应变MOSFET的半导体结构以及制造应变MOSFET的方法，其优化MOSFET中的应变，并且更特别地使MOSFET的一种（P或N）中的应变最大化并且使在另一种（N或P）MOSFET的应变中，在PMOSFET和NMOSFET两者上形成具有原始全厚度的A应变诱导氮化镓氮化物涂层，其中应变诱导涂层在一种半导体器件中产生优化的全应变，降低了另一种半导体器件的性能。诱导氮化钛涂层的应变被蚀刻到比另一种半导体器件更薄的厚度，其中应变诱导涂层的减小的厚度在其它MOSFET中松弛并产生较小的应变。

7. 发明申请

WO2012078225A1 STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs 审中-公开
标题翻译：具有高K /金属栅极MOSFET的调谐和短路控制的结构和方法
公开(公告)号：WO2012078225A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/051675
申请日：2011-09-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , WANG, Xinlin , CHEN, Xiangdong , CAI, Jin
发明人： WANG, Xinlin , CHEN, Xiangdong , CAI, Jin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate (12) having a well region 12B located within an upper region thereof. A semiconductor material stack (14) is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer (15) and a non-doped semiconductor-containing channel layer (16); the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack (18) located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer 20, a work function metal layer (22) and a polysilicon layer (24).
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区域12B的半导体衬底（12）。半导体材料堆（14）位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层（15）和非掺杂的含半导体的沟道层（16）; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠（18）。在本公开中采用的栅极材料叠层包括从底部到顶部的高k栅介质层20，功函数金属层（22）和多晶硅层（24）。

8. 发明申请

WO2011056391A3 HIGH-DRIVE CURRENT MOSFET 审中-公开
标题翻译：高驱动电流MOSFET
公开(公告)号：WO2011056391A3
公开(公告)日：2011-08-04
申请号：PCT/US2010052989
申请日：2010-10-18
申请人： IBM , PARK JAE-EUN , WANG XINLIN , CHEN XIANGDONG
发明人： PARK JAE-EUN , WANG XINLIN , CHEN XIANGDONG
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device 100 having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure 15 on a first portion of the substrate 5 having a well 35 of a first conductivity. A source region 20 of a second conductivity and drain region 25 of the second conductivity is formed within the well 35 of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region 30 of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件100的方法。在一个实施例中，该方法包括在具有第一导电性的阱35的基板5的第一部分上形成栅极结构15。在基板的与存在栅极结构的第一部分相邻的部分中，在第一导电体的阱35内形成具有第二导电性的第二导电和漏极区域25的源极区域20。在漏区内形成具有第二导电性的掺杂区域30，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性阱提供，基极由漏极第二电导率的区域和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

9. 发明申请

WO2006078740A3 STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETS 审中-公开
公开(公告)号：WO2006078740A3
公开(公告)日：2006-07-27
申请号：PCT/US2006/001768
申请日：2006-01-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHEN, Xiangdong , YANG, Haining, S.
发明人： CHEN, Xiangdong , YANG, Haining, S.
IPC分类号： H01L29/78 , H01L21/8238
摘要： A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

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