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1. 发明申请

WO2020113166A3 EARLY FUSION OF CAMERA AND RADAR FRAMES 审中-公开
公开(公告)号：WO2020113166A3
公开(公告)日：2020-06-04
申请号：PCT/US2019/063856
申请日：2019-11-29
申请人： QUALCOMM INCORPORATED
发明人： GOWAIKAR, Radhika Dilip , SUKHAVASI, Ravi Teja , FONTIJNE, Daniel Hendricus Franciscus , MAJOR, Bence , ANSARI, Amin , LIM, Teck Yian , SUBRAMANIAN, Sundar , WU, Xinzhou
IPC分类号： G01S13/931 , G01S13/86 , G01S13/89 , G06N3/02 , G01S7/295 , G06K9/00 , G06N3/04 , G01S7/41
摘要： Disclosed are techniques for fusing camera and radar frames to perform object detection in one or more spatial domains. In an aspect, an on-board computer of a host vehicle receives, from a camera sensor of the host vehicle, a plurality of camera frames, receives, from a radar sensor of the host vehicle, a plurality of radar frames, performs a camera feature extraction process on a first camera frame of the plurality of camera frames to generate a first camera feature map, performs a radar feature extraction process on a first radar frame of the plurality of radar frames to generate a first radar feature map, converts the first camera feature map and/or the first radar feature map to a common spatial domain, and concatenates the first radar feature map and the first camera feature map to generate a first concatenated feature map in the common spatial domain.

2. 发明申请

WO2017200667A1 SUPPLY VOLTAGE DROOP MANAGEMENT CIRCUITS FOR REDUCING OR AVOIDING SUPPLY VOLTAGE DROOPS 审中-公开
标题翻译：用于降低或避免供电电压的电源电压降低管理电路
公开(公告)号：WO2017200667A1
公开(公告)日：2017-11-23
申请号：PCT/US2017/027374
申请日：2017-04-13
申请人： QUALCOMM INCORPORATED
发明人： JAFFARI, Javid , ANSARI, Amin
IPC分类号： G06F1/30 , G06F1/32
摘要： Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.
摘要翻译：公开了用于降低或避免电源电压下降的电源电压下垂管理电路。电源电压下垂管理电路包括被配置为接收由功能电路生成的事件信号的中断电路。事件信号对应于在功能电路中发生的操作事件，并且增加对为功能电路供电的电源的负载电流需求，导致电源电压下降。中断电路被配置为响应于接收到的事件信号而产生中断信号。存储器包括具有与操作事件对应的目标频率的条目的操作事件频率表。以目标频率运行功能电路可降低电源上的负载电流需求，并降低电源电压下降。时钟控制电路被配置为接收中断信号，访问存储器以确定目标频率，并且生成时钟频率调整信号以使时钟发生器调整到目标频率。

3. 发明申请

WO2022256074A1 OBJECT DETECTION AND RANGING USING ONE-DIMENSIONAL RADAR ARRAYS 审中-公开
公开(公告)号：WO2022256074A1
公开(公告)日：2022-12-08
申请号：PCT/US2022/022850
申请日：2022-03-31
申请人： QUALCOMM INCORPORATED
发明人： SLOBODYANYUK, Volodimir , GOWAIKAR, Radhika Dilip , JOHN WILSON, Makesh Pravin , ANSARI, Amin , HAMILTON, Michael John , SANYAL, Shantanu Chaisson , SUBRAMANIAN, Sundar
IPC分类号： G01S13/42 , G01S13/931 , G01S13/02
摘要： In some aspects, a system may receive, from a first one-dimensional radar array, first information based at least in part on first reflections associated with an azimuthal plane. The system may further receive, from a second one-dimensional radar array, second information based at least in part on second reflections associated with an elevation plane. Accordingly, the system may detect an object based at least in part on the first information and may determine an elevation associated with the object based at least in part on the second information. Numerous other aspects are described.

4. 发明申请

WO2020113166A2 EARLY FUSION OF CAMERA AND RADAR FRAMES 审中-公开
公开(公告)号：WO2020113166A2
公开(公告)日：2020-06-04
申请号：PCT/US2019/063856
申请日：2019-11-29
申请人： QUALCOMM INCORPORATED
发明人： GOWAIKAR, Radhika Dilip , SUKHAVASI, Ravi Teja , FONTIJNE, Daniel Hendricus Franciscus , MAJOR, Bence , ANSARI, Amin , LIM, Teck Yian , SUBRAMANIAN, Sundar , WU, Xinzhou
IPC分类号： G01S13/931 , G01S13/86 , G01S13/89 , G06N3/02 , G01S7/295
摘要： Disclosed are techniques for fusing camera and radar frames to perform object detection in one or more spatial domains. In an aspect, an on-board computer of a host vehicle receives, from a camera sensor of the host vehicle, a plurality of camera frames, receives, from a radar sensor of the host vehicle, a plurality of radar frames, performs a camera feature extraction process on a first camera frame of the plurality of camera frames to generate a first camera feature map, performs a radar feature extraction process on a first radar frame of the plurality of radar frames to generate a first radar feature map, converts the first camera feature map and/or the first radar feature map to a common spatial domain, and concatenates the first radar feature map and the first camera feature map to generate a first concatenated feature map in the common spatial domain.

5. 发明申请

WO2017155662A1 MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY SYSTEM 审中-公开
标题翻译：混合并行串行存储器系统中的多级降级
公开(公告)号：WO2017155662A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/017191
申请日：2017-02-09
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , LI, Yanru , JAFFARI, Javid , ANSARI, Amin
IPC分类号： G06F12/02 , G06F13/16 , G11C7/10 , G06F12/10 , G06F12/1081 , G06F12/08 , G06F12/06
摘要： Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access region in a first memory rank and a dedicated parallel access region in a second memory rank. A request is received for a virtual memory page. If the request comprises a performance hint, the virtual memory page is selectively assigned to a free physical page in the dedicated serial access in the first memory rank and the dedicated parallel access region in the second memory rank.
摘要翻译：公开了用于在混合并行/串行存储器系统中分配存储器的系统，方法和计算机程序。一种方法包括为具有第一存储器列中的专用串行存取区域和第二存储器列中的专用并行存取区域的多列存储器系统配置存储器地址映射。接收到虚拟内存页面的请求。如果请求包括性能提示，则将虚拟存储器页选择性地分配给第一存储器列中的专用串行访问中的空闲物理页面和第二存储器列中的专用并行访问区域。

6. 发明申请

WO2020113160A3 RADAR DEEP LEARNING 审中-公开
公开(公告)号：WO2020113160A3
公开(公告)日：2020-06-04
申请号：PCT/US2019/063849
申请日：2019-11-29
申请人： QUALCOMM INCORPORATED
发明人： FONTIJNE, Daniel Hendricus Franciscus , ANSARI, Amin , MAJOR, Bence , SUKHAVASI, Ravi Teja , GOWAIKAR, Radhika Dilip , WU, Xinzhou , SUBRAMANIAN, Sundar , HAMILTON, Michael John
IPC分类号： G01S7/41 , G01S13/86 , G01S13/89 , G01S13/931 , G01S17/89 , G01S17/931 , G06N3/02 , G06K9/00 , G06N3/04
摘要： Disclosed are techniques for employing deep learning to analyze radar signals. In an aspect, an on-board computer of a host vehicle receives, from a radar sensor of the vehicle, a plurality of radar frames, executes a neural network on a subset of the plurality of radar frames, and detects one or more objects in the subset of the plurality of radar frames based on execution of the neural network on the subset of the plurality of radar frames. Further, techniques for transforming polar coordinates to Cartesian coordinates in a neural network are disclosed. In an aspect, a neural network receives a plurality of radar frames in polar coordinate space, a polar-to-Cartesian transformation layer of the neural network transforms the plurality of radar frames to Cartesian coordinate space, and the neural network outputs the plurality of radar frames in the Cartesian coordinate space.

7. 发明申请

WO2020113160A2 RADAR DEEP LEARNING 审中-公开
公开(公告)号：WO2020113160A2
公开(公告)日：2020-06-04
申请号：PCT/US2019/063849
申请日：2019-11-29
申请人： QUALCOMM INCORPORATED
发明人： FONTIJNE, Daniel Hendricus Franciscus , ANSARI, Amin , MAJOR, Bence , SUKHAVASI, Ravi Teja , GOWAIKAR, Radhika Dilip , WU, Xinzhou , SUBRAMANIAN, Sundar , HAMILTON, Michael John
IPC分类号： G01S7/41 , G01S13/86 , G01S13/89 , G01S13/931 , G01S17/89 , G01S17/931 , G06N3/02
摘要： Disclosed are techniques for employing deep learning to analyze radar signals. In an aspect, an on-board computer of a host vehicle receives, from a radar sensor of the vehicle, a plurality of radar frames, executes a neural network on a subset of the plurality of radar frames, and detects one or more objects in the subset of the plurality of radar frames based on execution of the neural network on the subset of the plurality of radar frames. Further, techniques for transforming polar coordinates to Cartesian coordinates in a neural network are disclosed. In an aspect, a neural network receives a plurality of radar frames in polar coordinate space, a polar-to-Cartesian transformation layer of the neural network transforms the plurality of radar frames to Cartesian coordinate space, and the neural network outputs the plurality of radar frames in the Cartesian coordinate space.

8. 发明申请

WO2019060670A1 COMPRESSION OF SPARSE DEEP CONVOLUTIONAL NETWORK WEIGHTS 审中-公开
公开(公告)号：WO2019060670A1
公开(公告)日：2019-03-28
申请号：PCT/US2018/052142
申请日：2018-09-21
申请人： QUALCOMM INCORPORATED
发明人： LAMB, Aaron , HILL, Rexford , ANSARI, Amin
IPC分类号： G06N3/063
摘要： The present disclosure describes methods, computer-readable media, and apparatuses for operating neural networks. For example, a first apparatus may receive a set of sparse weight vectors. The first apparatus may compress the set of sparse weight vectors to produce a compressed set of sparse weight vectors. The first apparatus may operate a neural network based on the compressed set of sparse weight vectors. In another example, a second apparatus may receive a set of sparse weight vectors. The second apparatus may perform a sparse computation based on the set of sparse weight vectors, and the performance of the sparse computation may produce one or more partial sums. The second apparatus may operate a neural network based at least in part on the one or more partial sums.

9. 发明申请

WO2018164762A1 MULTI-PROCESSOR CORE THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICS) (3DICS), AND RELATED METHODS 审中-公开
公开(公告)号：WO2018164762A1
公开(公告)日：2018-09-13
申请号：PCT/US2018/012077
申请日：2018-01-02
申请人： QUALCOMM INCORPORATED
发明人： SAMADI, Kambiz , ANSARI, Amin , DU, Yang
IPC分类号： G06F15/76 , H01L21/822 , H01L25/065 , H01L27/06
CPC分类号： G06F15/80 , G06F9/3012 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/382 , G06F9/384 , G06F9/3867 , G06F12/0875 , G06F15/76 , G06F15/803 , G06F2212/452 , H01L21/8221 , H01L25/0657 , H01L27/0688 , H01L2225/06513 , H01L2225/06541
摘要： Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores ("cores") to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

10. 发明申请

WO2017160480A1 PRIORITY-BASED ACCESS OF COMPRESSED MEMORY LINES IN MEMORY IN A PROCESSOR-BASED SYSTEM 审中-公开
标题翻译：在基于处理器的系统中，基于优先权的压缩存储器行访问内存
公开(公告)号：WO2017160480A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/018876
申请日：2017-02-22
申请人： QUALCOMM INCORPORATED
发明人： OPORTUS VALENZUELA, Andres, Alejandro , ANSARI, Amin , SENIOR, Richard , GENG, Nieyan , JANAKIRAMAN, Anand , CHHABRA, Gurvinder, Singh
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F3/0611 , G06F3/0626 , G06F3/0659 , G06F3/0661 , G06F3/0665 , G06F3/0673 , G06F12/023 , G06F12/0284 , G06F12/0615 , G06F12/0897 , G06F2212/1016 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/1056 , G06F2212/152 , G06F2212/401 , G06F2212/65
摘要： Aspects disclosed relate to a priority-based access of compressed memory lines in a processor-based system. In an aspect, a memory access device in the processor-based system receives a read access request for memory. If the read access request is higher priority, the memory access device uses the logical memory address of the read access request as the physical memory address to access the compressed memory line. However, if the read access request is lower priority, the memory access device translates the logical memory address of the read access request into one or more physical memory addresses in memory space left by the compression of higher priority lines. In this manner, the efficiency of higher priority compressed memory accesses is improved by removing a level of indirection otherwise required to find and access compressed memory lines.
摘要翻译：所公开的方面涉及基于处理器的系统中的压缩存储器行的基于优先级的访问。在一个方面，基于处理器的系统中的存储器访问设备接收对存储器的读访问请求。如果读访问请求的优先级较高，则存储器访问设备使用读访问请求的逻辑存储器地址作为物理存储器地址来访问压缩存储器行。然而，如果读取访问请求的优先级较低，则存储器访问设备将读取访问请求的逻辑存储器地址转换为由较高优先级行压缩留下的存储器空间中的一个或多个物理存储器地址。以这种方式，通过消除寻找和访问压缩存储器行所需的间接级别来提高较高优先级压缩存储器访问的效率。

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