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1. 发明申请

WO2006130466A3 A METHOD AND APPARATUS FOR PREDICTING BRANCH INSTRUCTIONS 审中-公开
标题翻译：一种用于预测分支指令的方法和装置
公开(公告)号：WO2006130466A3
公开(公告)日：2007-11-22
申请号：PCT/US2006020440
申请日：2006-05-24
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
IPC分类号： G06F9/42
CPC分类号： G06F9/3844
摘要： A microprocessor (10) includes two branch history tables, and is configured to use a first one (48) of the branch history tables for predicting branch instructions that are hits in a branch target cache (46), and to use a second one (50) of the branch history tables for predicting branch instructions that are misses in the branch target cache (46). As such, the first branch history table (48) is configured to have an access speed matched to that of the branch target cache (46), so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table (50) thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器（10）包括两个分支历史表，并且被配置为使用分支历史表中的第一个（48）来预测分支目标高速缓存（46）中的命中的分支指令，并且使用第二个分支指令 50）用于预测分支目标高速缓存（46）中未命中的分支指令的分支历史表。因此，第一分支历史表（48）被配置为具有与分支目标高速缓存（46）的访问速度相匹配的访问速度，使得其预测信息相对于可能发生的早期的分支目标高速缓存命中检测而及时可用在微处理器的指令管道中。因此，第二分支历史表（50）仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

2. 发明申请

WO2006125220A3 HANDLING CACHE MISS IN AN INSTRUCTION CROSSING A CACHE LINE BOUNDARY 审中-公开
标题翻译：在指令中处理高速缓存中的错误交叉缓存线路边界
公开(公告)号：WO2006125220A3
公开(公告)日：2007-05-10
申请号：PCT/US2006019789
申请日：2006-05-18
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
发明人： STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译：处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。指令可能会跨越缓存行边界。流水线处理两个地址以恢复完整的边界交叉指令。在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。

3. 发明申请

WO2006096568A3 POWER SAVING METHODS AND APPARATUS FOR VARIABLE LENGTH INSTRUCTIONS 审中-公开
标题翻译：节能方法和设备可变长度指示
公开(公告)号：WO2006096568A3
公开(公告)日：2007-01-11
申请号：PCT/US2006007758
申请日：2006-03-03
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
发明人： STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在标记行中存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

4. 发明申请

WO2006057907A3 PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION 审中-公开
标题翻译：通过分支校正进行预解码错误处理
公开(公告)号：WO2006057907A3
公开(公告)日：2006-12-14
申请号：PCT/US2005041850
申请日：2005-11-18
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as "mispredicted not taken" with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在其中指令在被存储在高速缓冲存储器中之前进行预解码的流水线处理器中，在流水线执行期间检测到不正确的预解码指令。相应的指令在高速缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被预测”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。重新读取的指令然后被正确地预解码，写入高速缓存并执行。

5. 发明申请

WO2006096569A3 FORWARD LOOKING BRANCH TARGET ADDRESS CACHING 审中-公开
标题翻译：前瞻性分支目标地址缓存
公开(公告)号：WO2006096569A3
公开(公告)日：2006-12-21
申请号：PCT/US2006007759
申请日：2006-03-03
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F9/32 , G06F12/08
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译：流水线处理器包括指令缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC中提取的阶段。为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC获取从iCache获取的分支指令的数量与从BTAC获取所需的周期相关。所公开的示例或者递减BTAC的写地址或者增加BTAC的提取地址的量基本上对应于比BTAC提取所需的周期小的量。

6. 发明申请

WO2007143508A3 SLIDING-WINDOW, BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：滑动窗口，基于块的分支目标地址高速缓存
公开(公告)号：WO2007143508A3
公开(公告)日：2008-01-31
申请号：PCT/US2007070111
申请日：2007-05-31
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

7. 发明申请

WO2008016849A3 METHOD AND APPARATUS FOR PREFETCHING NON-SEQUENTIAL INSTRUCTION ADDRESSES 审中-公开
标题翻译：用于预置非顺序指令地址的方法和装置
公开(公告)号：WO2008016849A3
公开(公告)日：2008-04-10
申请号：PCT/US2007074598
申请日：2007-07-27
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE
发明人： STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中未命中并作为提取操作的一部分访问较高阶存储器，并且与第一指令地址或第一指令地址之后的地址相关联的分支指令被检测并被预测得到，则预取在高阶存储器访问期间使用预测的分支目标地址来执行操作。如果在预取操作期间预测的分支目标地址在指令高速缓存中命中，则不检索相关联的指令以节省电力。如果在预取操作期间预测的分支目标地址在指令高速缓存中未命中，则可以使用预测的分支指令地址来启动更高阶的存储器访问。在任何一种情况下，第一个指令地址都会被重新载入到提取阶段的流水线中，以等待指令从其高阶内存访问中返回。

8. 发明申请

WO2006060198A9 TRANSLATION LOOKASIDE BUFFER (TLB) ACCESS SUPRESSION FOR INTRA-PAGE PROGRAM COUNTER RELATIVE OR ABSOLUTE ADDRESS BRANCH INSTRUCTIONS 审中-公开
标题翻译：翻译LOOKASIDE BUFFER（TLB）访问权限用于内部程序计数器相对或绝对地址分支指令
公开(公告)号：WO2006060198A9
公开(公告)日：2006-12-14
申请号：PCT/US2005041998
申请日：2005-11-17
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
发明人： DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
IPC分类号： G06F9/32 , G06F1/32 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA位于同一页面中，那么如BTSP位所指示的那样，对BTA的TLB访问检查权限属性被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

9. 发明申请

WO2006125219A2 CACHING INSTRUCTIONS FOR A MULTIPLE-STATE PROCESSOR 审中-公开
标题翻译：多状态处理器的缓存指令
公开(公告)号：WO2006125219A2
公开(公告)日：2006-11-23
申请号：PCT/US2006019788
申请日：2006-05-18
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A block of instructions may be retrieved from memory while the processor is operating in one of the states. The instructions may be pre-decoded in accordance with said one of the states and loaded into cache. The processor, or another entity, may be used to determine whether the current state of the processor is the same as said one of the states used to pre-decode the instructions when one of the pre-decoded instructions in the cache is needed by the processor.
摘要翻译：一种用于缓存具有多个操作状态的处理器的指令的方法和装置。处理器的至少两个操作状态支持不同的指令集。当处理器在其中一个状态下操作时，可以从存储器检索指令块。指令可以根据所述一种状态被预先解码并加载到高速缓存中。处理器或另一个实体可以用于确定处理器的当前状态是否与用于在高速缓存中的预解码指令之一由高速缓存中的一个预解码指令需要时用于对指令进行预解码的状态相同处理器。

10. 发明申请

WO2008021828A3 BRANCH PREDICTION USING A BRANCH TARGET ADDRESS CACHE IN A PROCESSOR WITH A VARIABLE LENGTH INSTRUCTION SET 审中-公开
标题翻译：在具有可变长度指令集的处理器中使用分支目标地址高速缓存的分支预测
公开(公告)号：WO2008021828A3
公开(公告)日：2009-10-22
申请号：PCT/US2007075363
申请日：2007-08-07
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , SMITH RODNEY WAYNE
发明人： STEMPEL BRIAN MICHAEL , SMITH RODNEY WAYNE
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30149 , G06F9/3806 , G06F9/3848
摘要： In a variable-length instruction set wherein the length of each instruction is a multiple of a minimum instruction length granularity, an indication of the last granularity (i.e., the end) of a taken branch instruction is a stored in a branch target address cache (BTAC). If a branch instruction that later hits in the BTAC is predicted taken, previously fetched instructions are flushed from the pipeline beginning immediately past the indicated end of the branch instruction. This technique saves BTAC space by avoiding to the need to store the length of the branch instruction in the BTAC, and improves performance by eliminating the necessity of calculating where to begin flushing (based on the length of the branch instruction).
摘要翻译：在每个指令的长度是最小指令长度粒度的倍数的可变长度指令集中，所采集的分支指令的最后粒度（即，结束）的指示被存储在分支目标地址高速缓存中 BTAC）。如果预测了后来在BTAC中命中的分支指令，则先前获取的指令从直接从分支指令的指示末端开始的流水线刷新。这种技术通过避免需要在BTAC中存储分支指令的长度来节省BTAC空间，并且通过消除计算在哪里开始刷新（基于分支指令的长度）的必要性来提高性能。

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