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1. 发明申请

WO2006130466A3 A METHOD AND APPARATUS FOR PREDICTING BRANCH INSTRUCTIONS 审中-公开
标题翻译：一种用于预测分支指令的方法和装置
公开(公告)号：WO2006130466A3
公开(公告)日：2007-11-22
申请号：PCT/US2006020440
申请日：2006-05-24
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
IPC分类号： G06F9/42
CPC分类号： G06F9/3844
摘要： A microprocessor (10) includes two branch history tables, and is configured to use a first one (48) of the branch history tables for predicting branch instructions that are hits in a branch target cache (46), and to use a second one (50) of the branch history tables for predicting branch instructions that are misses in the branch target cache (46). As such, the first branch history table (48) is configured to have an access speed matched to that of the branch target cache (46), so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table (50) thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器（10）包括两个分支历史表，并且被配置为使用分支历史表中的第一个（48）来预测分支目标高速缓存（46）中的命中的分支指令，并且使用第二个分支指令 50）用于预测分支目标高速缓存（46）中未命中的分支指令的分支历史表。因此，第一分支历史表（48）被配置为具有与分支目标高速缓存（46）的访问速度相匹配的访问速度，使得其预测信息相对于可能发生的早期的分支目标高速缓存命中检测而及时可用在微处理器的指令管道中。因此，第二分支历史表（50）仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

2. 发明申请

WO2006096568A3 POWER SAVING METHODS AND APPARATUS FOR VARIABLE LENGTH INSTRUCTIONS 审中-公开
标题翻译：节能方法和设备可变长度指示
公开(公告)号：WO2006096568A3
公开(公告)日：2007-01-11
申请号：PCT/US2006007758
申请日：2006-03-03
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
发明人： STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在标记行中存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

3. 发明申请

WO2006057907A3 PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION 审中-公开
标题翻译：通过分支校正进行预解码错误处理
公开(公告)号：WO2006057907A3
公开(公告)日：2006-12-14
申请号：PCT/US2005041850
申请日：2005-11-18
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as "mispredicted not taken" with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在其中指令在被存储在高速缓冲存储器中之前进行预解码的流水线处理器中，在流水线执行期间检测到不正确的预解码指令。相应的指令在高速缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被预测”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。重新读取的指令然后被正确地预解码，写入高速缓存并执行。

4. 发明申请

WO2006096569A3 FORWARD LOOKING BRANCH TARGET ADDRESS CACHING 审中-公开
标题翻译：前瞻性分支目标地址缓存
公开(公告)号：WO2006096569A3
公开(公告)日：2006-12-21
申请号：PCT/US2006007759
申请日：2006-03-03
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F9/32 , G06F12/08
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译：流水线处理器包括指令缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC中提取的阶段。为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC获取从iCache获取的分支指令的数量与从BTAC获取所需的周期相关。所公开的示例或者递减BTAC的写地址或者增加BTAC的提取地址的量基本上对应于比BTAC提取所需的周期小的量。

5. 发明申请

WO2006086713A2 CONDITIONAL INSTRUCTION EXECUTION VIA EMISSARY INSTRUCTION FOR CONDITION EVALUATION 审中-公开
标题翻译：条件指导执行条件评估的动态指示
公开(公告)号：WO2006086713A2
公开(公告)日：2006-08-17
申请号：PCT/US2006004892
申请日：2006-02-10
申请人： QUALCOMM INC , MCILVAINE MICHAEL SCOTT , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE
发明人： MCILVAINE MICHAEL SCOTT , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译：通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。在基本指令停止的情况下执行执行指令。使者指令评估条件并将条件评估报告回基本指令。基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP，或者是一个空指令，代替它）。在任一情况下，可以解决以下指令的依赖性。

6. 发明申请

WO2006113420A3 SYSTEM AND METHOD WHEREIN CONDITIONAL INSTRUCTIONS UNCONDITIONALLY PROVIDE OUTPUT 审中-公开
标题翻译：条件指令的系统和方法无条件地提供输出
公开(公告)号：WO2006113420A3
公开(公告)日：2006-12-21
申请号：PCT/US2006014042
申请日：2006-04-14
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , DOCKSER KENNETH ALAN , MCILVAINE MICHAEL SCOTT , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , DOCKSER KENNETH ALAN , MCILVAINE MICHAEL SCOTT , SMITH RODNEY WAYNE
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
摘要翻译：一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便它无条件地向目标提供输出。条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。评估条件。如果满足条件，则执行操作，并将操作结果输出到目标。如果条件不满足，则将先前值输出到目标。后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

7. 发明申请

WO2006102635A3 BRANCH TARGET ADDRESS CACHE STORING TWO OR MORE BRANCH TARGET ADDRESSES PER INDEX 审中-公开
标题翻译：分支目标地址高速缓存存储两个或更多分支目标每个索引地址
公开(公告)号：WO2006102635A3
公开(公告)日：2007-02-15
申请号：PCT/US2006010952
申请日：2006-03-23
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A Branch Target Address Cache (BTAC) stores at least two branch target addresses in each cache line. The BTAC is indexed by a truncated branch instruction address. An offset obtained from a branch prediction offset table determines which of the branch target addresses is taken as the predicted branch target address. The offset table may be indexed in several ways, including by a branch history, by a hash of a branch history and part of the branch instruction address, by a gshare value, randomly, in a round-robin order, or other methods.
摘要翻译：分支目标地址缓存（BTAC）在每个高速缓存行中存储至少两个分支目标地址。 BTAC由截断的分支指令地址索引。从分支预测偏移表获得的偏移决定了哪个分支目标地址被作为预测分支目标地址。偏移表可以通过分支历史，分支历史和部分分支指令地址的散列，以循环次序或其他方法随机的gshare值被索引。

8. 发明申请

WO2006084288A3 INSTRUCTION PREFETCH MECHANISM 审中-公开
标题翻译：指导性机制
公开(公告)号：WO2006084288A3
公开(公告)日：2007-01-11
申请号：PCT/US2006006993
申请日：2006-02-03
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , AUGSBURG VICTOR ROBERT , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , MCILVAINE MICHAEL SCOTT , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , AUGSBURG VICTOR ROBERT , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , MCILVAINE MICHAEL SCOTT , SMITH RODNEY WAYNE
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译：处理器包括产生加权分支预测值的条件分支指令预测机制。对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。或者，可以从高速缓存中继续预取。为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

9. 发明申请

WO2006089188A3 METHOD AND APPARATUS FOR MANAGING A RETURN STACK 审中-公开
标题翻译：管理回收堆栈的方法和装置
公开(公告)号：WO2006089188A3
公开(公告)日：2007-01-04
申请号：PCT/US2006005775
申请日：2006-02-17
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.
摘要翻译：处理器包括用于预测用于指令预取的过程返回地址的返回堆栈电路，其中返回堆栈控制器确定与给定返回指令相关联的返回水平的数量，并且从返回堆栈中弹出该返回地址的数量。从返回堆栈弹出多个返回地址允许处理器在连续的过程调用链中预取原始调用过程的返回地址。在一个实施例中，返回堆栈控制器从嵌入在返回指令中的值读取返回电平的数量。补充编译器计算给定返回指令的返回值，并在编译时将这些值嵌入到它们中。在另一个实施例中，返回栈电路通过对连续过程调用链中的过程调用（分支）进行计数来动态地跟踪返回电平的数量。

10. 发明申请

WO2007143508A3 SLIDING-WINDOW, BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：滑动窗口，基于块的分支目标地址高速缓存
公开(公告)号：WO2007143508A3
公开(公告)日：2008-01-31
申请号：PCT/US2007070111
申请日：2007-05-31
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

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