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1. 发明申请

WO2006051490A1 FREQUENCY DIVISION BY ODD INTEGERS 审中-公开
标题翻译： ODD整数的频率划分
公开(公告)号：WO2006051490A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053679
申请日：2005-11-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W.
发明人： VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W.
IPC分类号： H03K23/48
CPC分类号： H03K23/483
摘要： The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CLl) frequency by an odd integer. A digital value is shifted into a set of latches based on the clock signal (CLl) and kept there a predetermined number of half clock cycles. The value is shifted into a following latch delayed with half a clock cycle of the clock signal compared with a previous latch. Then a first (Ql) and a second (Q6) intermediate signal, each provided through information stored in a latch, are interpolated for forming said first output signal (O Q). Because of this it is possible to provide an output signal having edges displaced from clock signal edges, thus allowing a higher resolution than the original clock signal has and in particular, enabling quadrature outputs from a standard odd-integer frequency divider.
摘要翻译：本发明涉及一种用于提供具有通过将时钟信号（CL1）频率除以奇整数而获得的频率的至少第一输出信号（O Q）的方法和装置。数字值根据时钟信号（CL1）移入一组锁存器，并保持预定数量的半个时钟周期。与先前的锁存器相比，该值被移位到延迟了时钟信号的半个时钟周期的后续锁存器。然后插入通过存储在锁存器中的信息提供的第一（Q1）和第二（Q6）中间信号，以形成所述第一输出信号（O Q）。因此，可以提供具有从时钟信号边缘移位的边缘的输出信号，从而允许比原始时钟信号具有更高的分辨率，并且特别地，允许来自标准奇整数分频器的正交输出。

2. 发明申请

WO2006075288A1 FREQUENCY-HOPPING ARRANGEMENT 审中-公开
标题翻译：频率偏好安排
公开(公告)号：WO2006075288A1
公开(公告)日：2006-07-20
申请号：PCT/IB2006/050084
申请日：2006-01-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W.
发明人： VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W.
IPC分类号： H04B1/713
CPC分类号： H03L7/183 , H04B1/7136 , H04B1/7163 , H04B2001/71365
摘要： A frequency-hopping arrangement comprises a basic-frequency branch (DIVl), an offset-frequency branch (DIV2, DIV3, SCC), and a controllable frequency converter (SBM, FSC). The basic-frequency branch (DIVl) receives an oscillator signal (OS) having an oscillator-signal frequency (7920MHz). The basic-frequency branch has a frequency-division factor (/2) so as to provide a basic-frequency signal (BF) having a basic frequency (+3960MHz) that is the oscillator-signal frequency divided by the frequency- division factor. The offset-frequency branch (DIV2, DIV3, SCC) receives the same oscillator signal (OS). The offset-frequency branch has a different frequency-division factor (/3, /5) so as to provide an offset-frequency signal (OF) having an offset frequency (+528MHz) that is the oscillator-signal frequency divided by the different frequency-division factor. The controllable frequency converter (SBM, FSC) provides a frequency-hopping signal (FHS) having a frequency (cl*+3960 + c2*+528 MHz) that is a linear combination of the basic frequency and the offset frequency with at least one coefficient (c2) that varies as a function of a hopping-control signal (HCS).
摘要翻译：跳频装置包括基频分支（DIV1），偏移频分支（DIV2，DIV3，SCC）和可控变频器（SBM，FSC）。基频分支（DIV1）接收具有振荡器信号频率（7920MHz）的振荡器信号（OS）。基频分频具有分频因子（/ 2），以便提供基频（+ 3960MHz）的基频信号（BF），其中振荡信号频率除以分频系数。偏移频率分支（DIV2，DIV3，SCC）接收相同的振荡器信号（OS）。偏移频率分支具有不同的分频因子（/ 3，/ 5），以便提供具有偏移频率（+ 528MHz）的偏移频率信号（OF），该偏移频率信号是振荡器信号频率除以不同的分频因子。可控频率转换器（SBM，FSC）提供具有频率（cl * + 3960 + c2 * + 528MHz）的频率跳频信号（FHS），其是基本频率和偏移频率的线性组合，并具有至少一个系数（c2）随跳频控制信号（HCS）的变化而变化。

3. 发明申请

WO2005101680A1 DEVICE FOR EXCHANGING ULTRA WIDE BAND SIGNALS 审中-公开
标题翻译：用于交换超宽带信号的设备
公开(公告)号：WO2005101680A1
公开(公告)日：2005-10-27
申请号：PCT/IB2005/051203
申请日：2005-04-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W. , BERGERVOET, Jozef, R., M.
发明人： VAN DE BEEK, Remco, C., H. , LEENAERTS, Dominicus, M., W. , BERGERVOET, Jozef, R., M.
IPC分类号： H04B1/69
CPC分类号： H04B1/71635 , H03D3/007 , H04B1/71637 , H04L27/2647
摘要： Devices (1-4) for exchanging ultra wide band signals are provided with highfrequency stages (5,6) for tuning the devices (1-4) to ultra wide bands and with lowfrequency stages (7-10) for tuning the devices (1-4) to frequency channels of the ultra wide bands. This way, the tuning to the frequency channels of the ultra wide band is shifted from (prior art situation) the high-frequency stage to (invention) the low-frequency stage, and can be done in a fast and distortionless way. The high-frequency stages (5,6) comprise highfrequency mixers (51,52,61,62) for frequency translating signals by applying a highfrequency oscillation signal per ultra wide band. The low-frequency stages (7-10) comprise either low-frequency mixers (81-84,101-104) for frequency translating signals by applying a low-frequency oscillation signal per frequency channel, or comprise converters (70-72,90-92) having a bandwidth larger than a bandwidth of combined frequency channels of the ultra wide band. The device (1-4) comprises a receiver/transmitter, and may be a terminal/station device of a frequency hopping network.
摘要翻译：用于交换超宽带信号的设备（1-4）设置有用于将设备（1-4）调谐到超宽带和低频级（7-10）的高频级（5,6），用于调谐设备（1 -4）到超宽频带的频道。这样，对超宽频带的频道的调谐从高频级（现有技术情况）向低频级转变为（发明型），可以以快速，无失真的方式进行。高频级（5,6）包括用于通过每超宽带施加高频振荡信号来频率转换信号的高频混频器（51,52,61,62）。低频级（7-10）包括用于频率转换信号的低频混频器（81-84,101-104），每个频道施加低频振荡信号，或包括转换器（70-72,90-92 ）具有比超宽带的组合频道的带宽大的带宽。设备（1-4）包括接收机/发射机，并且可以是跳频网络的终端/站设备。

4. 发明申请

WO2004021574A1 PHASE LOCKED LOOP 审中-公开
标题翻译：相位锁定环
公开(公告)号：WO2004021574A1
公开(公告)日：2004-03-11
申请号：PCT/IB2003/003726
申请日：2003-07-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco, C., H. , KLUMPERINK, Eric, A., M. , NAUTA, Bram , VAUCHER, Cicero, S.
发明人： VAN DE BEEK, Remco, C., H. , KLUMPERINK, Eric, A., M. , NAUTA, Bram , VAUCHER, Cicero, S.
IPC分类号： H03L7/089
CPC分类号： H03L7/191 , H03D13/00 , H03L7/087 , H03L7/089 , H03L7/0893 , H03L7/113
摘要： A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).
摘要翻译：一种锁相环，包括用于确定参考信号（Ref）和相互相移信号（I，Q）之间的相位差的相位检测器（100），以产生频率控制信号（U，D），相位检测器（100）包括：用于通过参考信号（Ref）和相对相移信号（I，Q）之一的二进制相乘来获得所述频率控制信号（U，D）中的第一个的装置（10）。以及用于通过相对相移信号（I，Q）的二进制相乘来获得所述频率控制信号（U，D）中的第二个的装置（20）。

5. 发明申请

WO2008122958A3 HIGH-FREQUENCY COUNTER 审中-公开
标题翻译：高频计数器
公开(公告)号：WO2008122958A3
公开(公告)日：2008-12-04
申请号：PCT/IB2008051332
申请日：2008-04-08
申请人： NXP BV , VAN DE BEEK REMCO C H
发明人： VAN DE BEEK REMCO C H
IPC分类号： H03K5/135 , H03K23/58 , H03L7/091 , H03L7/113
CPC分类号： H03K5/135 , H03K23/588 , H03L7/113 , H03L7/18 , H03L2207/50
摘要： The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance witha state- cycle, and a second counting section is clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the at least one invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.
摘要翻译：计数器电路和控制这种计数器电路的方法技术领域本发明涉及计数器电路和控制这种计数器电路的方法，其中第一计数部分根据状态周期进行计数，并且第二计数部分由第一计数部分计时。在第一计数部分完成状态循环之前，通过控制第二计数部分改变其状态来引入至少一个无效计数状态; 然后检测并校正至少一个无效计数状态。因此，计数器中引入了一些冗余，可用于检测和纠正计数器状态的不完整切换。

6. 发明申请

WO2003065586A3 PHASE-LOCKED-LOOP WITH REDUCED CLOCK JITTER 审中-公开
公开(公告)号：WO2003065586A3
公开(公告)日：2003-08-07
申请号：PCT/IB2003/000130
申请日：2003-01-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
发明人： NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
IPC分类号： H03L7/197
摘要： The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

7. 发明申请

WO03065586A2 PHASE-LOCKED-LOOP WITH REDUCED CLOCK JITTER 审中-公开
标题翻译：带有减速时钟抖动器的锁相环
公开(公告)号：WO03065586A2
公开(公告)日：2003-08-07
申请号：PCT/IB0300130
申请日：2003-01-20
申请人： KONINKL PHILIPS ELECTRONICS NV , NAUTA BRAM , VAN DE BEEK REMCO C H , VAUCHER CICERO S
发明人： NAUTA BRAM , VAN DE BEEK REMCO C H , VAUCHER CICERO S
IPC分类号： H03L7/18 , H03L7/089 , H03L7/095 , H03L7/107 , H03L7/197
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/107 , H03L7/197
摘要： The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
摘要翻译：锁相环（PLL）电路及其控制方法技术领域本发明涉及锁相环（PLL）电路和控制这种PLL电路的方法，其中输入参考信号的频率和从输出振荡信号导出的反馈信号的频率除以从而降低PLL电路的相位检测装置（1）的频率。响应于PLL电路的锁相状态的检测，禁止分频步骤。因此，在实现了相位锁定之后，从循环中除去添加了减小比较频率的额外的参考分频器（6），从而能够增加环路带宽并减小环路内的分频比。

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