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    • 3. 发明申请
    • INTRUSION PROTECTION USING STRESS CHANGES
    • 使用压力变化的侵入保护
    • WO2009150558A1
    • 2009-12-17
    • PCT/IB2009/052184
    • 2009-05-26
    • NXP B.V.HOOFMAN, RomanoPIJNENBURG, Remco Henricus WilhelmusPONOMAREV, Youri Victorovitch
    • HOOFMAN, RomanoPIJNENBURG, Remco Henricus WilhelmusPONOMAREV, Youri Victorovitch
    • G06F21/00H01L23/58G06K19/073
    • H01L23/576G06F21/87H01L2924/0002H01L2924/00
    • The invention relates to a integrated circuit comprising an electronic circuit integrated on a substrate (5), and further comprising protections means for protection of the electronic circuit (25). The protection means comprise: i) a first strained encapsulation layer (10) being provided on a first side of the substrate (5), wherein the first strained encapsulation layer (10) has a strain (Sl) in a direction parallel to the substrate (5), and ii) disabling means (20) arranged for at least partially disabling the electronic circuit (25) under control of a strain change in the substrate (5). The invention further relates to a method of manufacturing such integrated circuit, and to a system comprising such integrated circuit. Such system is selected from a group comprising: a bank-card, a smart-card, a contact-less card and an RFID. All embodiments of the integrated circuit in accordance with the invention provide essentially an alternative tamper protection to the data stored or present in the electronic circuit therein. A first main group of embodiments concerns an integrated circuit wherein tamper protection is obtained by detecting a strain change during tampering and subsequently disabling the electronic circuit. A second main group of embodiments concerns an integrated circuit wherein tamper protection is obtained by designing a stack of strained encapsulation layers, such that tampering causes releasing of strain and thereby mechanical disintegrate (break, delaminate, etc) of the integrated circuit, and thus disabling the electronic circuit.
    • 本发明涉及一种集成电路,其包括集成在基板(5)上的电子电路,并且还包括用于保护电子电路(25)的保护装置。 保护装置包括:i)第一应变封装层(10),设置在基板(5)的第一侧上,其中第一应变封装层(10)在平行于基板的方向上具有应变(S1) (5),以及ii)布置成在所述衬底(5)中的应变变化的控制下至少部分地禁用所述电子电路(25)的禁用装置(20)。 本发明还涉及一种制造这种集成电路的方法,以及包括这种集成电路的系统。 这样的系统从包括银行卡,智能卡,无接触卡和RFID的组中选择。 根据本发明的集成电路的所有实施例基本上为存储或存在于其中的电子电路中的数据提供了替代的篡改保护。 第一主要实施例涉及集成电路,其中通过在篡改期间检测应变变化并随后禁用电子电路来获得篡改保护。 第二主要实施例涉及一种集成电路,其中通过设计应变封装层的堆叠来获得防篡改,使得篡改导致应变释放,从而导致集成电路的机械分解(破坏,分层等),从而导致无效 电子电路。
    • 4. 发明申请
    • CHARGE-PUMP CIRCUIT
    • 充电电路
    • WO2010070603A1
    • 2010-06-24
    • PCT/IB2009/055812
    • 2009-12-17
    • NXP B.V.CURATOLA, GilbertoPONOMAREV, Youri Victorovitch
    • CURATOLA, GilbertoPONOMAREV, Youri Victorovitch
    • H02M3/07
    • H02M3/073H02M3/07
    • - The invention describes a charge-pump circuit (1, 1') comprising a supply voltage input node (10) for applying an input voltage (U in ) to be boosted, a boosted voltage output node (11) for outputting a boosted voltage (U out ), and a plurality of transistor stages connected in series between the supply voltage input node (10) and the boosted voltage output node (11), wherein at least one transistor stage comprises a multiple-gate transistor (D1,..., D5), which transistor (D1,..., D5) comprises at least two gates, of which one is a first gate (G) for switching the transistor (D1,..., D5) on or off according to a voltage applied to the first gate (G), and one is an additional second gate (G i ) for controlling the threshold voltage of the multiple-gate transistor (D1,..., D5), independently of the first gate (G), according to a control voltage (Φ1, Φ2) applied to the second gate (G i ). The invention further describes a method of boosting a voltage using a charge-pump circuit (1, 1') comprising a plurality of transistor stages connected in series between a supply voltage input node (10) and a boosted voltage output node (11), wherein at least one transistor stage comprises a multiple- gate transistor (D1,..., D5), which method comprises applying an input voltage (U in ) to be boosted at the supply voltage input node (10); applying a control voltage (Φ1, Φ2) to the second gate (G i ) of the multiple-gate transistor (D1,..., D5) to control the threshold voltage of the multiple-gate transistor (D1,..., D5); and outputting the boosted voltage (U out ) at the voltage output node (11).
    • - 本发明描述了一种电荷泵电路(1,1'),其包括用于施加要升压的输入电压(Uin)的电源电压输入节点(10),用于输出升压电压的升压电压输出节点(11) Uout)和串联连接在电源电压输入节点(10)和升压电压输出节点(11)之间的多个晶体管级,其中至少一个晶体管级包括多栅晶体管(D1,..., D5),哪个晶体管(D1,...,D5)包括至少两个栅极,其中一个是用于根据电压开关晶体管(D1,...,D5)导通或截止的第一栅极(G) 施加到第一栅极(G),并且一个是用于独立于第一栅极(G)控制多栅极晶体管(D1,...,D5)的阈值电压的另外的第二栅极(Gi),根据 到施加到第二门(Gi)的控制电压(F1,F2)。 本发明还描述了一种使用包括串联连接在电源电压输入节点(10)和升压电压输出节点(11)之间的多个晶体管级的电荷泵电路(1,1')来提升电压的方法, 其中至少一个晶体管级包括多栅极晶体管(D1,...,D5),该方法包括在电源电压输入节点(10)处施加要升压的输入电压(Uin); 将控制电压(F1,F2)施加到多栅极晶体管(D1,...,D5)的第二栅极(Gi),以控制多栅极晶体管(D1,...,D5)的阈值电压 ); 并输出在电压输出节点(11)处的升压电压(Uout)。