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1. 发明申请

WO2010042365A3 ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING 审中-公开
标题翻译：用于存储器编程的架构和方法
公开(公告)号：WO2010042365A3
公开(公告)日：2010-06-03
申请号：PCT/US2009059009
申请日：2009-09-30
申请人： MICRON TECHNOLOGY INC , VALI TOMMASO , SANTIN GIOVANNI , INCARNATI MICHELE , MOSCHIANO VIOLANTE
发明人： VALI TOMMASO , SANTIN GIOVANNI , INCARNATI MICHELE , MOSCHIANO VIOLANTE
IPC分类号： G11C16/34 , G11C16/02 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

2. 发明申请

WO2012135060A3 NON-VOLATILE MEMORY PROGRAMMING 审中-公开
标题翻译：非易失性存储器编程
公开(公告)号：WO2012135060A3
公开(公告)日：2012-12-06
申请号：PCT/US2012030430
申请日：2012-03-23
申请人： MICRON TECHNOLOGY INC , MOSCHIANO VIOLANTE , SANTIN GIOVANNI , INCARNATI MICHELE
发明人： MOSCHIANO VIOLANTE , SANTIN GIOVANNI , INCARNATI MICHELE
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26
CPC分类号： G11C16/34 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.
摘要翻译：一些实施例包括存储设备和对存储设备的存储单元进行编程的方法。一种这样的方法可以包括将信号施加到与存储器单元相关联的线，该信号是基于数字信息生成的。该方法还可以包括，当信号被施加到线时，确定在数字信息具有第一值时存储器单元的状态是否接近目标状态，以及确定存储器单元的状态是否已经达到目标当数字信息具有第二值时状态。描述了包括附加存储器设备和方法的其他实施例。

3. 发明申请

WO2009111158A3 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 审中-公开
标题翻译：存储设备编程中的电荷损失补偿
公开(公告)号：WO2009111158A3
公开(公告)日：2009-11-19
申请号：PCT/US2009034270
申请日：2009-02-17
申请人： MICRON TECHNOLOGY INC , MOSCHIANO VIOLANTE , INCARNATI MICHELE , SANTIN GIOVANNI , ORLANDI DANILO
发明人： MOSCHIANO VIOLANTE , INCARNATI MICHELE , SANTIN GIOVANNI , ORLANDI DANILO
IPC分类号： G11C16/34 , G11C16/10 , G11C16/12
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译：所选字线上的所选存储单元通过多个编程脉冲被编程，所述多个编程脉冲被递增阶跃电压。在成功的编程验证操作之后，所选存储器单元的编程被禁止，而所选字线的其他存储器单元正被编程。在选定的存储单元上执行另一个编程验证操作。如果编程验证操作失败，耦合到所选单元的位线在步进电压处被偏置，并且最终编程脉冲被发送到所选字线。然后锁定所选择的存储单元而不进行进一步编程，而不评估最终的编程验证操作。

4. 发明申请

WO02069347A3 FLASH CELL FUSE CIRCUIT 审中-公开
标题翻译：闪存电池保险丝电路
公开(公告)号：WO02069347A3
公开(公告)日：2003-03-20
申请号：PCT/US0205735
申请日：2002-02-27
申请人： MICRON TECHNOLOGY INC
发明人： SANTIN GIOVANNI , NASO GIOVANNI
IPC分类号： G11C16/20 , G11C16/26 , G11C17/18 , G11C29/00
CPC分类号： G11C29/789 , G11C16/0441 , G11C16/20 , G11C16/26 , G11C17/18
摘要： Fuse circuits (300) based on a single flash cell or floating-gate memory cell (305) are adapted for use in memory devices (201), particularly in low-voltage, flash memory applications. The fuse circuits (300) include a floating-gate memory cell (305) for storing a data value and a fuse latch (360) to hold and transfer the data value of the floating-gate memory cell (305) at power-up or upon request. A latch driver circuit (400) can write data values to the fuse latch (360) without affecting the data value stored in the floating-gate memory cell (305). The fuse circuits (300) can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array (205). As the fuse circuits (300) can utilize the same structure and organization, the data value of the fuse circuit (300) can be programmed, erased and read using the same data path (325) as the regular memory array (205).
摘要翻译：基于单个闪存单元或浮动栅极存储单元（305）的保险丝电路（300）适于在存储器件（201）中使用，特别是在低电压闪速存储器应用中。熔丝电路（300）包括用于存储数据值的浮栅存储单元（305）和熔断器锁存器（360），以在上电时保持和传送浮栅存储单元（305）的数据值，或者根据要求。锁存器驱动器电路（400）可以将数据值写入熔丝锁存器（360）而不影响存储在浮动栅极存储单元（305）中的数据值。熔丝电路（300）可进一步利用与存储器件存储器阵列（205）相同的结构，间距，位线组织和字线组织。当熔丝电路（300）可以利用相同的结构和组织时，可以使用与常规存储器阵列（205）相同的数据路径（325）对熔丝电路（300）的数据值进行编程，擦除和读取。

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