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1. 发明申请

WO2006031280A2 PROBE ARRAYS AND METHOD FOR MAKING 审中-公开
标题翻译：探索阵列和制作方法
公开(公告)号：WO2006031280A2
公开(公告)日：2006-03-23
申请号：PCT/US2005/023706
申请日：2005-06-30
申请人： MICROFABRICA INC. , KUMAR, Ananda, H. , KRUGLICK, Ezekiel, J., J. , COHEN, Adam, L. , KIM, Kieun , ZHANG, Gang , CHEN, Richard, T. , BANG, Christopher, A. , ARAT, Vacit , LOCKARD, Michael, S. , FRODIS, Uri , LEMBRIKOV, Pavel, B. , THOMPSON, Jeffrey, A.
发明人： KUMAR, Ananda, H. , KRUGLICK, Ezekiel, J., J. , COHEN, Adam, L. , KIM, Kieun , ZHANG, Gang , CHEN, Richard, T. , BANG, Christopher, A. , ARAT, Vacit , LOCKARD, Michael, S. , FRODIS, Uri , LEMBRIKOV, Pavel, B. , THOMPSON, Jeffrey, A.
IPC分类号： G01R31/02
CPC分类号： G01R1/07378 , G01R1/06744 , G01R3/00 , H01L23/66 , H01L2224/0554 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/09701 , H01L2924/18165 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
摘要翻译：本发明的实施例涉及在临时衬底上形成微探针（即柔性电气或电子接触元件），切割各个探针阵列，然后将阵列转移到空间变压器或其它永久衬底。在将探针从其上形成探针的临时基底分离出来之前，本发明的一些实施例将探针转移到永久性基底上，而其他实施方案相反。一些实施例，在转移之前去除牺牲材料，而其它实施例在转移之后去除牺牲材料。一些实施例涉及使用一个或多个具有增强的纵横比（即，高度与宽度比）的焊料凸块将第一和第二电气部件结合在一起的结果，所述焊料凸块至少部分地由保持材料的环围绕凸块。保留材料可以用作焊接掩模材料。

2. 发明申请

WO2005065431A2 MICROPROBE TIPS AND METHODS FOR MAKING 审中-公开
标题翻译： MICROPROBE提示和制作方法
公开(公告)号：WO2005065431A2
公开(公告)日：2005-07-21
申请号：PCT/US2005/000301
申请日：2005-01-03
申请人： MICROFABRICA INC. , KIM, Kieun , COHEN, Adam, L. , LARSEN, Willa, M. , CHEN, Richard, T. , KUMAR, Ananda, H. , KRUGLICK, Ezekiel, J., J. , ARAT, Vacit , ZHANG, Gang , LOCKARD, Michael, S. , BANG, Christopher, A. , THOMPSON, Jeffrey, A.
发明人： KIM, Kieun , COHEN, Adam, L. , LARSEN, Willa, M. , CHEN, Richard, T. , KUMAR, Ananda, H. , KRUGLICK, Ezekiel, J., J. , ARAT, Vacit , ZHANG, Gang , LOCKARD, Michael, S. , BANG, Christopher, A. , THOMPSON, Jeffrey, A.
IPC分类号： G01R3/00 , G01R31/02
CPC分类号： G01R3/00
摘要： Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the lame building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate. Probe tip patterning may occur in a variety of different ways, including, for example, via molding in patterned holes that have been isotropically or anisotropically etched silicon, via molding in voids formed in over exposed photoresist, via molding in voids in a sacrificial material that have formed as a result of the sacrificial material mushrooming over carefully sized and located regions of dielectric material, via isotropic etching of a the tip material around carefully sized placed etching shields, via hot pressing, and the like.
摘要翻译：本发明的实施例涉及形成具有各种构造的微探针尖元件。在一些实施例中，尖端由作为探针本身的跛脚建筑材料形成，而在其它实施例中，尖端可以由不同的材料形成和/或可以包括涂层材料。在一些实施例中，尖端在探针的主要部分之前形成，并且尖端形成在临时衬底附近或与临时衬底接触。探针尖端图案化可以以各种不同的方式发生，包括例如通过在各向异性或各向异性地蚀刻硅的图案化孔中模制，通过在暴露在光致抗蚀剂中的空隙中模制，通过在牺牲材料中的空隙中模制，由于牺牲材料在电介质材料的精细尺寸和定位的区域上的形成，通过各种各向同性的蚀刻尖端材料，围绕小心尺寸放置的蚀刻屏蔽件，通过热压等形成。

3. 发明申请

WO2005065430A2 ELECTROCHEMICAL FABRICATION METHODS FOR PRODUCING MULTILAYER STRUCTURES INCLUDING THE USE OF DIAMOND MACHINING IN THE PLANARIZATION OF DEPOSITS OF MATERIAL 审中-公开
标题翻译：用于生产多层结构的电化学制造方法，包括在材料沉积物平面化中使用金刚石加工
公开(公告)号：WO2005065430A2
公开(公告)日：2005-07-21
申请号：PCT/US2005/000165
申请日：2005-01-03
申请人： MICROFABRICA INC. , COHEN, Adam, L. , FRODIS, Uri , LOCKARD, Michael, S. , KUMAR, Ananda, H. , ZHANG, Gang , SMALLEY, Dennis, R.
发明人： COHEN, Adam, L. , FRODIS, Uri , LOCKARD, Michael, S. , KUMAR, Ananda, H. , ZHANG, Gang , SMALLEY, Dennis, R.
IPC分类号： B05D1/38 , C08K3/00 , C25D3/30 , C25D3/38 , C25D3/48 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/288 , H01L21/301 , H01L21/302 , H01L21/4763 , H01L21/768
CPC分类号： C25D5/48 , B33Y10/00 , B81C1/00492 , B81C99/0065 , B81C2201/0104 , B81C2201/0197 , C25D1/00 , C25D1/003 , C25D5/022 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L21/76885 , Y10T156/1052
摘要： Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining ( e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear ( e.g. Ni-P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn-Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials ( e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level ( e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete the process, and/or forming structures or portions of structures from thin walled regions of hard-to-machine materials as opposed to wide solid regions of structural material.
摘要翻译：公开了用于形成单层和多层中尺度和微结构的电化学制造方法，其包括使用金刚石加工（例如飞切或车削）来平坦化层。一些实施例集中于可用于电化学制造的牺牲和结构材料的系统，并且可以以最小的工具磨损（例如，Ni-P和Cu，Au和Cu，Cu和Sn，Au和Cu，Au和Sn，和Au和Sn-Pb），其中第一材料或材料是结构材料，第二材料是牺牲材料）。一些实施例着重于在使用金刚石加工以平面化使用难以加工的材料进行电化学制造的结构（例如，通过沉积难以机械材料选择性且潜在地具有少量多余电镀厚度和/或预加工沉积到所需表面水平的小增量（例如使用研磨或粗切割操作），然后使用金刚石飞切切割来完成该工艺，和/或从硬质材料的薄壁区域形成结构或部分结构而不是结构材料的宽固体区域。

4. 发明申请

WO2005065433A2 ELECTROCHEMICAL FABRICATION METHODS INCORPORATING DIELECTRIC MATERIALS AND/OR USING DIELECTRIC SUBSTRATES 审中-公开
标题翻译：电介质材料和/或使用电介质基板的电化学制造方法
公开(公告)号：WO2005065433A2
公开(公告)日：2005-07-21
申请号：PCT/US2005/000061
申请日：2005-01-03
申请人： MICROFABRICA INC. , COHEN, Adam, L. , LOCKARD, Michael, S. , KIM, Kieun , LE, Qui, T. , ZHANG, Gang , FRODIS, Uri , MCPHERSON, Dale, S. , SMALLEY, Dennis, R.
发明人： COHEN, Adam, L. , LOCKARD, Michael, S. , KIM, Kieun , LE, Qui, T. , ZHANG, Gang , FRODIS, Uri , MCPHERSON, Dale, S. , SMALLEY, Dennis, R.
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23C18/16 , C23F1/00 , C25D5/02 , C25D5/10 , C25D5/34 , H01L21/288 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： B44C1/22 , B33Y10/00 , B81C1/00492 , C03C15/00 , C03C25/68 , C23C18/1605 , C23C18/161 , C23C18/1651 , C23C18/1653 , C23C18/405 , C23F1/00 , C25D1/003 , C25D5/02 , C25D5/10 , H01L21/2885 , H01L21/44 , H01L21/4763 , H01L21/76885
摘要： Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.
摘要翻译：本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。在一些实施方案中，电介质材料是可UV固化的光聚合物。

5. 发明申请

WO2012119123A2 TEMPERATURE COMPENSATION AND COARSE TUNE BANK SWITCHES IN A LOW PHASE NOISE VCO 审中-公开
标题翻译：低相位噪声压控振荡器中的温度补偿和谐波调节银行开关
公开(公告)号：WO2012119123A2
公开(公告)日：2012-09-07
申请号：PCT/US2012/027603
申请日：2012-03-02
申请人： QUALCOMM INCORPORATED , ZHANG, Gang
发明人： ZHANG, Gang
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L1/02 , H03L7/104
摘要： The LC tank of a VCO includes a main varactor circuit and temperature compensation varactor circuit coupled in parallel with the main varactor circuit. The main varactor is used for fine tuning. The temperature compensation varactor circuit has a capacitance- voltage characteristic that differs from a capacitance-voltage characteristic of the main varactor circuit such that the effects of common mode noise across the two varactor circuits are minimized. The LC tank also has a plurality of switchable capacitor circuits provided for coarse tuning. To prevent breakdown of the main thin oxide switch in each of the switchable capacitor circuits, each switchable capacitor circuit has a capacitive voltage divider circuit that reduces the voltage across the main thin oxide switch when the main switch is off.
摘要翻译： VCO的LC箱包括与主变容二极管并联耦合的主变容二极管电路和温度补偿变容二极管电路。主变容器用于微调。温度补偿变容二极管的电容电压特性与主变容二极管电路的电容 - 电压特性不同，使两个变容二极管之间的共模噪声的影响最小化。 LC箱还具有用于粗调的多个可切换电容器电路。为了防止每个可切换电容器电路中的主薄氧化物开关的破坏，每个可切换电容器电路具有电容分压器电路，当主开关断开时，电容分压电路降低主薄氧化物开关两端的电压。

6. 发明申请

WO2010042764A1 LOW-POWER ASYNCHRONOUS COUNTER AND METHOD 审中-公开
标题翻译：低功率异步计数器和方法
公开(公告)号：WO2010042764A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/060063
申请日：2009-10-08
申请人： QUALCOMM INCORPORATED , ZHANG, Gang
发明人： ZHANG, Gang
IPC分类号： H03K21/12
CPC分类号： H03L7/183 , H03K21/12 , H03L2207/50
摘要： Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).
摘要翻译：低功耗异步计数器的设计技术。在示例性实施例中，多个触发器的时钟输入和信号输出串联连接以实现异步计数机制。多个触发器的信号输出通过参考信号的连续延迟版本进行采样。公开了用于产生参考信号的连续延迟版本的进一步的设计技术。在示例性实施例中，可以在用于数字锁相环（DPLL）的高速计数器中使用异步计数技术。

7. 发明申请

WO2010017274A1 ACCUMULATED PHASE-TO-DIGITAL CONVERSION IN DIGITAL PHASE LOCKED LOOPS 审中-公开
标题翻译：数字相位锁定中的累积相数转换
公开(公告)号：WO2010017274A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/052813
申请日：2009-08-05
申请人： QUALCOMM INCORPORATED , ZHANG, Gang
发明人： ZHANG, Gang
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/1976 , H03L2207/50
摘要： Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by- N module that divides the frequency of the signal down by a divider ratio N. The divided signal is input to a delta phase-to-digital converter, which measures the phase difference between a rising edge of the divided signal and a rising edge of a reference signal. The accumulated divider ratios and the measured phase differences are combined to give an accumulated digital phase. Further techniques for varying the divider ratio N using a sigmato- delta modulator are disclosed.
摘要翻译：用于将信号的累积相位转换为数字锁相环（DPLL）中的数字值的技术。在示例性实施例中，信号被耦合到N分频模块，其将信号的频率下降除以分频比N.分频信号被输入到Δ相位数转换器，其测量相位分频信号的上升沿与参考信号的上升沿之间的差。累积的分频比和测量的相位差被组合以产生累积的数字相位。公开了使用Sigmato-delta调制器改变分频比N的其它技术。

8. 发明申请

WO2009129258A1 PHASE TO DIGITAL CONVERTER IN ALL DIGITAL PHASE LOCKED LOOP 审中-公开
标题翻译：相位数字转换器在所有数字相位锁定环路
公开(公告)号：WO2009129258A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/040555
申请日：2009-04-14
申请人： QUALCOMM INCORPORATED , ZHANG, Gang , JAJOO, Abishek , HAN, Yiping
发明人： ZHANG, Gang , JAJOO, Abishek , HAN, Yiping
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/089 , H03L7/1976 , H03L2207/50
摘要： A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.
摘要翻译：这里描述了一个相数转换器，全数字锁相环和具有全数字锁相环的装置。相数转换器包括驱动时间到数字转换器的相位到频率转换器。数字转换器的时间决定了相位变频器输出的相位差的大小和符号。数字转换器的时间利用抽头延迟线和环路反馈计数器来测量环路跟踪过程中典型的小时序差异以及循环获取过程的典型时序差。抽头延迟线允许测量参考周期的分数，并通过减少对参考时钟速度的要求，实现相位数字转换器的低功耗操作。

9. 发明申请

WO2009108815A1 DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译： DELTA-SIGMA调制器时钟在一个分段N相锁定环路
公开(公告)号：WO2009108815A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/035349
申请日：2009-02-26
申请人： QUALCOMM Incorporated , XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
发明人： XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
IPC分类号： H03L7/197
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.
摘要翻译：在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。在一个示例中，PLL包括新颖的可编程时钟抖动电路。可编程时钟抖动电路可通过串行总线进行控制，以选择的几种方式对时钟信号的相位进行抖动。如果时钟信号以第一种方式抖动（伪随机相位抖动），则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展，从而降低噪声干扰其他电路的程度。如果时钟信号以第二种方式抖动（旋转相位抖动），则数字噪声的功率被频移，使得噪声干扰另一电路的程度降低。可编程时钟抖动电路可以以其他方式进行控制。例如，抖动可以可编程地禁用。

10. 发明申请

WO2009036221A1 OSCILLATOR SIGNAL GENERATION WITH SPUR MITIGATION IN A WIRELESS COMMUNICATION DEVICE 审中-公开
标题翻译：振荡器信号发生在无线通信设备中的缓和
公开(公告)号：WO2009036221A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/076085
申请日：2008-09-11
申请人： QUALCOMM Incorporated , KIM, Hong Sun , KIM, Jin Wook , ZHANG, Gang , DUNWORTH, Jeremy Darren , PALS, Timothy Paul
发明人： KIM, Hong Sun , KIM, Jin Wook , ZHANG, Gang , DUNWORTH, Jeremy Darren , PALS, Timothy Paul
IPC分类号： H03L7/107 , H03L7/193 , H03L7/197
CPC分类号： H03L7/193 , H03L7/107 , H03L7/1976
摘要： Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.
摘要翻译：描述了在无线通信设备中产生振荡器信号的技术。可以使用锁相环（PLL）来产生所选频道的振荡器信号。对于不同的频率通道，PLL中的块可能使用不同的PLL设置。不同的PLL设置可能是针对不同的PLL环路带宽，不同的电荷泵浦电流量，与不同的高和低分频比组相关的不同频率方程，与不同的预分频比和/或不同的整数分频比相关的不同分频方案，用于超外差接收器或发射器的高侧或低侧注入，和/或用于一个或多个电路块（例如振荡器）的不同电源电压。可以为每个频道选择合适的一组PLL设置，从而可以减轻由于刺激引起的不利影响。

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