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1. 发明申请

WO2009129258A1 PHASE TO DIGITAL CONVERTER IN ALL DIGITAL PHASE LOCKED LOOP 审中-公开
标题翻译：相位数字转换器在所有数字相位锁定环路
公开(公告)号：WO2009129258A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/040555
申请日：2009-04-14
申请人： QUALCOMM INCORPORATED , ZHANG, Gang , JAJOO, Abishek , HAN, Yiping
发明人： ZHANG, Gang , JAJOO, Abishek , HAN, Yiping
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/089 , H03L7/1976 , H03L2207/50
摘要： A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.
摘要翻译：这里描述了一个相数转换器，全数字锁相环和具有全数字锁相环的装置。相数转换器包括驱动时间到数字转换器的相位到频率转换器。数字转换器的时间决定了相位变频器输出的相位差的大小和符号。数字转换器的时间利用抽头延迟线和环路反馈计数器来测量环路跟踪过程中典型的小时序差异以及循环获取过程的典型时序差。抽头延迟线允许测量参考周期的分数，并通过减少对参考时钟速度的要求，实现相位数字转换器的低功耗操作。

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