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1. 发明申请

WO2022035467A1 INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTURE 审中-公开
公开(公告)号：WO2022035467A1
公开(公告)日：2022-02-17
申请号：PCT/US2021/018154
申请日：2021-02-16
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SATO, Justin , CHEN, Bomy , LENG, Yaojian , MARSICO, Gerald , KOVATS, Julius
IPC分类号： H01L21/60 , H01L23/485
摘要： An integrated circuit device may include a multi-material toothed bond pad (306, 406, 770, 940, 1102, 1202) including (a) an array of vertically-extending teeth (320, 420, 720, 904, 1110, 1204) formed from a first material and (b) a second material (fill material) (322, 422, 760, 930, 1112, 1206) at least partially filling voids (724, 906, 1206) between the array of teeth (320, 420, 720, 904, 1110, 1204). The teeth (320, 420, 720, 904, 1110, 1204) may be formed by depositing and etching the first material and the fill material (322, 422, 760, 930, 1112, 1206) may be deposited over the array of teeth (320, 420, 720, 904, 1110, 1204) and extending down into the voids (724, 906, 1206) between the teeth (320, 420, 720, 904, 1110, 1204), and etched to expose top surfaces of the teeth (320, 420, 720, 904, 1110, 1204). The array of teeth (320, 420, 720, 904, 1110, 1204) may collectively define an abrasive structure. The multi-material toothed bond pad (306, 406, 770, 940, 1102, 1202) may be bonded to another bond pad (304, 404, 1142, 1222), e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth (320, 420, 720) may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad (304, 306, 404, 406, 770) surfaces, to thereby create a direct and/or eutectic bonding between the bond pads (304, 306, 404, 406, 770). The teeth (320, 420, 720) may comprise oxidized teeth (324, 424, 754) including an oxide layer (312, 412, 764) formed on each tooth (320, 420, 720), wherein the oxide layer (312, 412, 764) formed on each tooth (320, 420, 720) may define the abrasive structure. The teeth (720) may include silicon nodules at an exposed surface of the tooth (720). A roughening process may be performed to increase a surface roughness of the teeth (320, 324, 420, 424, 720, 754). The integrated circuit device may comprise an interposer (203, 402, 700, 900, 1100, 1200) and/or an integrated circuit die (300, 400a, 400b, 1140a, 1140b, 1220). The first material may comprise aluminum and the second material (322, 422, 760, 930, 1112, 1206) may comprise silver. Alternatively, the first material may comprise silicon. A bond pad (1142) configured to bond with a toothed bond pad (1102) may have a three-dimensional shape designed to further improve bonding with the toothed bond pad (1102), e.g., a three-dimensional shape including recesses or other geometries configured to receive the teeth (1110) of the toothed bond pad (1102); in particular, each bond pad (1142) may include a plurality of protrusions (1144) that define openings or voids (1146) configured to receive the teeth (1110), wherein the protrusions (1144) may be tapered, rounded, or otherwise configured to facilitate a self-alignment of each bond pad (1142) with a corresponding bond pad (1102). Metal bumps (e.g., gold stud bumps (1230)) may be applied to the bond pads (1222) that engage with the multi-material toothed bond pads (1202), wherein the multi-material toothed bond pads (1202) may be fully covered by an underfill region (1210), e.g., comprising epoxy.

2. 发明申请

WO2018151988A1 NON-VOLATILE FLASH MEMORY CELL 审中-公开
公开(公告)号：WO2018151988A1
公开(公告)日：2018-08-23
申请号：PCT/US2018/017233
申请日：2018-02-07
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： DARYANANI, Sonu , CHEN, Bomy , HYMAS, Mel
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L27/11521
摘要： A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-poly layer; and patterning and etching the second polysilicon layer to separate the second polysilicon layer into word line devices and erase gates.

3. 发明申请

WO2023023257A2 INTEGRATED CIRCUIT PACKAGE WITH HEAT TRANSFER CHIMNEY INCLUDING THERMALLY CONDUCTIVE NANOPARTICLES 审中-公开
公开(公告)号：WO2023023257A2
公开(公告)日：2023-02-23
申请号：PCT/US2022/040769
申请日：2022-08-18
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： CHEN, Bomy , SATO, Justin
IPC分类号： H01L23/367 , H01L23/373 , H01L23/433 , H01L23/29 , H01L23/31 , H01L23/552 , H01L23/556
摘要： An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.

4. 发明申请

WO2021216143A1 BACKSIDE INTERCONNECT FOR INTEGRATED CIRCUIT PACKAGE INTERPOSER 审中-公开
公开(公告)号：WO2021216143A1
公开(公告)日：2021-10-28
申请号：PCT/US2021/013023
申请日：2021-01-12
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SATO, Justin , LENG, Yaojian , CHEN, Bomy , SUNDAHL, Chris
IPC分类号： H01L23/498 , H01L21/762 , H01L23/538
摘要： Methods are provided for forming an integrated circuit (IC) package interposer configured for back-side attachment. A porous silicon double layer is formed on a bulk silicon wafer, e.g., using a controlled anodization, the porous silicon double layer including two porous silicon layers having different porosities. An interposer is formed over the porous silicon double layer, the interposer including back-side contacts, front-side contacts, and conductive structures (e.g., vias and metal interconnect) extending through the interposer to connect selected back-side contacts with selected front-side contacts. The structure is then split at the interface between the first and second porous silicon layers of the silicon double layer, and the interposer including the second porous silicon layers is inverted and etched to remove the second silicon layer and expose the back-side contacts, such that the exposed back-side contacts can be used for back-side attachment of the interposer to a package substrate or other structure.

5. 发明申请

WO2014158754A1 RESISTIVE MEMORY CELL WITH REDUCED BOTTOM ELECTRODE 审中-公开
标题翻译：具有降低底电极的电阻记忆体
公开(公告)号：WO2014158754A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/019868
申请日：2014-03-03
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： DARYANANI, Sonu , CHEN, Bomy
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/145
摘要： A resistive memory cell (100) includes a ring-shaped bottom electrode (102), a top electrode (108), and an electrolyte layer (106) arranged between the bottom and top electrodes. A ring-shaped bottom electrode is formed by forming a dielectric layer (104) over a bottom electrode contact, etching a via in the dielectric layer to expose at least a portion of the bottom electrode contact, depositing a conductive via liner over the dielectric layer and into the via, the via liner deposited in the via forming a ring-shaped structure in the via and a contact portion in contact with the exposed bottom electrode contact, the ring-shaped structure defining a radially inward cavity of the ring-shaped structure, and filling the cavity with a dielectric fill material, such that the ring-shaped structure of the via liner forms the ring-shaped bottom electrode, depositing an electrolyte layer over the bottom electrode, and depositing a top electrode over the electrolyte layer.
摘要翻译：电阻式存储单元（100）包括环形底部电极（102），顶部电极（108）和布置在底部和顶部电极之间的电解质层（106）。通过在底部电极接触件上形成电介质层（104）形成环形底部电极，蚀刻电介质层中的通孔以暴露底部电极接触的至少一部分，在电介质层上沉积导电通孔衬垫并且进入通孔中，沉积在通孔中的通孔衬垫在通孔中形成环形结构，以及与暴露的底部电极接触件接触的接触部分，环形结构限定环形结构的径向向内的腔并且用电介质填充材料填充空腔，使得通孔衬垫的环形结构形成环形底部电极，在底部电极上沉积电解质层，并在电解质层上沉积顶部电极。

6. 发明申请

WO2015108903A1 HIGH VOLTAGE DOUBLE-DIFFUSED MOS ( DMOS) DEVICE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：高电压双通道MOS（DMOS）器件及其制造方法
公开(公告)号：WO2015108903A1
公开(公告)日：2015-07-23
申请号：PCT/US2015/011299
申请日：2015-01-14
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： CHEN, Bomy , DARYANANI, Sonu
IPC分类号： H01L27/115 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/66
CPC分类号： H01L29/7816 , G11C16/0408 , G11C16/06 , H01L21/2652 , H01L21/266 , H01L23/552 , H01L27/11524 , H01L27/11543 , H01L29/0653 , H01L29/0856 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66674 , H01L29/66681 , H01L29/66825 , H01L29/7801 , H01L29/7883 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated DMOS transistor / EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.
摘要翻译：形成集成的DMOS晶体管/ EEPROM单元的方法包括在衬底上形成第一掩模，使用第一掩模在衬底中形成漂移注入以对准漂移注入，同时在漂移注入上形成第一浮栅，以及与所述漂移注入件间隔开的第二浮动栅极，形成覆盖所述第二浮动栅极并覆盖所述第一浮动栅极的一部分的第二掩模，使用所述第一浮动栅极的边缘在所述基板中形成基底注入以使所述基底并且同时在第一浮动栅极上形成第一控制栅极，并且在第二浮栅上方形成第二控制栅极。第一浮栅，第一控制栅，漂移注入和基极注入形成DMOS晶体管的组件，第二浮栅和第二控制栅形成EEPROM单元的组件。

7. 发明申请

WO2023086119A1 VAPOR CELLS AND RELATED SYSTEMS AND METHODS 审中-公开
公开(公告)号：WO2023086119A1
公开(公告)日：2023-05-19
申请号：PCT/US2022/017521
申请日：2022-02-23
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LUTWAK, Robert , CHEN, Bomy
IPC分类号： G04F5/14 , H03L7/26
摘要： Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smalltest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.

8. 发明申请

WO2021206760A1 INTEGRATED CIRCUIT (IC) PACKAGE WITH INTEGRATED INDUCTOR HAVING CORE MAGNETIC FIELD (B FIELD) EXTENDING PARALLEL TO DIE SUBSTRATE 审中-公开
公开(公告)号：WO2021206760A1
公开(公告)日：2021-10-14
申请号：PCT/US2020/063201
申请日：2020-12-04
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian , SATO, Justin , CHEN, Bomy
IPC分类号： H01L23/64 , H01L25/065 , H01L25/18
摘要： An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

9. 发明申请

WO2020247009A1 FLASH MEMORY CELL ADAPTED FOR LOW VOLTAGE AND/OR NON-VOLATILE PERFORMANCE 审中-公开
公开(公告)号：WO2020247009A1
公开(公告)日：2020-12-10
申请号：PCT/US2019/052835
申请日：2019-09-25
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： DARYANANI, Sonu , CHEN, Bomy , MARTIN, Matthew
IPC分类号： G11C16/04 , H01L27/115
摘要： A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ?6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to "RAM Flash" memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

10. 发明申请

WO2019178035A1 INTEGRATED CIRCUIT (IC) DEVICE INCLUDING A FORCE MITIGATION SYSTEM FOR REDUCING UNDER-PAD DAMAGE CAUSED BY WIRE BOND 审中-公开
公开(公告)号：WO2019178035A1
公开(公告)日：2019-09-19
申请号：PCT/US2019/021767
申请日：2019-03-12
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SATO, Justin , CHEN, Bomy , TAYLOR, Andrew
IPC分类号： H01L23/00
摘要： An integrated circuit chip die includes a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding below each wire bond pad. The force mitigation system includes a metal region (22) serving as a shock plate, a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids (56A) between the metal region (22) and the sealing layer (52). The sealed voids (56A) in the force mitigation layer are defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer (52) over the openings to define an array of sealed voids (56A). The force mitigation system mitigates stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

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