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1. 发明申请

WO2023038668A1 METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE 审中-公开
公开(公告)号：WO2023038668A1
公开(公告)日：2023-03-16
申请号：PCT/US2022/019669
申请日：2022-03-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian
IPC分类号： H01L49/02 , H01L23/522
摘要： A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.

2. 发明申请

WO2022260701A1 CARBON NANOTUBE (CNT) MEMORY CELL ELEMENT AND METHODS OF CONSTRUCTION 审中-公开
公开(公告)号：WO2022260701A1
公开(公告)日：2022-12-15
申请号：PCT/US2021/062152
申请日：2021-12-07
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian
IPC分类号： H01L45/00
摘要： Carbon nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements are provided. A CNT memory cell may comprise a CNT memory cell element, e.g., in combination with a transistor. A CNT memory cell element (202) includes a metal/CNT layer/metal (M/CNT/M) structure (220, 222, 224) formed between adjacent metal interconnect layers (Mx, Mx+i) or between a silicided active layer (e.g., including MOSFET devices) and a metal interconnect layer. The M/CNT/M structure is formed by a process including forming a tub opening (213) in a dielectric region (208), forming a cup-shaped bottom electrode (220) in the tub opening, forming a cup-shaped CNT layer (222) in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode (224) in an interior opening defined by the cup-shaped CNT layer.

3. 发明申请

WO2023043485A1 INTEGRATED CIRCUIT STRUCTURE INCLUDING A METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE AND A THIN-FILM RESISTOR (TFR) MODULE 审中-公开
公开(公告)号：WO2023043485A1
公开(公告)日：2023-03-23
申请号：PCT/US2022/019450
申请日：2022-03-09
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian
IPC分类号： H01L27/06 , H01L27/07 , H01L49/02
摘要： An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

4. 发明申请

WO2022146486A1 THIN-FILM RESISTOR (TFR) WITH IMPROVED CONTACTS 审中-公开
公开(公告)号：WO2022146486A1
公开(公告)日：2022-07-07
申请号：PCT/US2021/039563
申请日：2021-06-29
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian , SATO, Justin
IPC分类号： H01L49/02 , H01L23/522
摘要： A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extending laterally between the TFR side contacts, and first and second TFR element end flanges projecting vertically from opposing ends of the base portion. The first TFR element end flange is formed on a sidewall of the first TFR side contact, and the second TFR element end flange is formed on a sidewall of the second TFR side contact. A first TFR head contacts the first TFR side contact and a top of the first TFR element end flange, and a second TFR head contacts the second TFR side contact and a top of the second TFR element end flange, thus defining two parallel conductive paths between the TFR element and each TFR head.

5. 发明申请

WO2021011019A1 TECHNIQUES FOR MAKING INTEGRATED INDUCTORS AND RELATED SEMICONDUCTOR DEVICES, ELECTRONIC SYSTEMS, AND METHODS 审中-公开
公开(公告)号：WO2021011019A1
公开(公告)日：2021-01-21
申请号：PCT/US2019/047911
申请日：2019-08-23
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian
IPC分类号： H01L49/02
摘要： In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design.

6. 发明申请

WO2019241094A1 ALUMINUM COMPATIBLE THIN-FILM RESISTOR (TFR) AND MANUFACTURING METHODS 审中-公开
公开(公告)号：WO2019241094A1
公开(公告)日：2019-12-19
申请号：PCT/US2019/036242
申请日：2019-06-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SATO, Justin Hiroki , LENG, Yaojian , STOM, Gregory Allen
IPC分类号： H01L49/02
摘要： A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure may include forming a trench in a dielectric region; forming a TFR element in the trench, the TFR element including a laterally-extending TFR region and a TFR ridge extending upwardly from a laterally-extending TFR region; depositing at least one metal layer over the TFR element; and patterning the at least one metal layer and etching the at least one metal layer using a metal etch to define a pair of metal TFR heads over the TFR element, wherein the metal etch also removes at least a portion of the upwardly-extending TFR ridge. The method may also include forming at least one conductive TFR contact extending through the TFR element and in contact with a respective TFR head to thereby increase a conductive path between the respective TFR head and the TFR element.

7. 发明申请

WO2022086595A1 METAL-OXIDE-METAL (MOM) CAPACITORS FOR INTEGRATED CIRCUIT MONITORING 审中-公开
公开(公告)号：WO2022086595A1
公开(公告)日：2022-04-28
申请号：PCT/US2021/032721
申请日：2021-05-17
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian , SATO, Justin
IPC分类号： G01R31/28 , G01R31/64 , H01L21/66
摘要： An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

8. 发明申请

WO2022035467A1 INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTURE 审中-公开
公开(公告)号：WO2022035467A1
公开(公告)日：2022-02-17
申请号：PCT/US2021/018154
申请日：2021-02-16
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SATO, Justin , CHEN, Bomy , LENG, Yaojian , MARSICO, Gerald , KOVATS, Julius
IPC分类号： H01L21/60 , H01L23/485
摘要： An integrated circuit device may include a multi-material toothed bond pad (306, 406, 770, 940, 1102, 1202) including (a) an array of vertically-extending teeth (320, 420, 720, 904, 1110, 1204) formed from a first material and (b) a second material (fill material) (322, 422, 760, 930, 1112, 1206) at least partially filling voids (724, 906, 1206) between the array of teeth (320, 420, 720, 904, 1110, 1204). The teeth (320, 420, 720, 904, 1110, 1204) may be formed by depositing and etching the first material and the fill material (322, 422, 760, 930, 1112, 1206) may be deposited over the array of teeth (320, 420, 720, 904, 1110, 1204) and extending down into the voids (724, 906, 1206) between the teeth (320, 420, 720, 904, 1110, 1204), and etched to expose top surfaces of the teeth (320, 420, 720, 904, 1110, 1204). The array of teeth (320, 420, 720, 904, 1110, 1204) may collectively define an abrasive structure. The multi-material toothed bond pad (306, 406, 770, 940, 1102, 1202) may be bonded to another bond pad (304, 404, 1142, 1222), e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth (320, 420, 720) may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad (304, 306, 404, 406, 770) surfaces, to thereby create a direct and/or eutectic bonding between the bond pads (304, 306, 404, 406, 770). The teeth (320, 420, 720) may comprise oxidized teeth (324, 424, 754) including an oxide layer (312, 412, 764) formed on each tooth (320, 420, 720), wherein the oxide layer (312, 412, 764) formed on each tooth (320, 420, 720) may define the abrasive structure. The teeth (720) may include silicon nodules at an exposed surface of the tooth (720). A roughening process may be performed to increase a surface roughness of the teeth (320, 324, 420, 424, 720, 754). The integrated circuit device may comprise an interposer (203, 402, 700, 900, 1100, 1200) and/or an integrated circuit die (300, 400a, 400b, 1140a, 1140b, 1220). The first material may comprise aluminum and the second material (322, 422, 760, 930, 1112, 1206) may comprise silver. Alternatively, the first material may comprise silicon. A bond pad (1142) configured to bond with a toothed bond pad (1102) may have a three-dimensional shape designed to further improve bonding with the toothed bond pad (1102), e.g., a three-dimensional shape including recesses or other geometries configured to receive the teeth (1110) of the toothed bond pad (1102); in particular, each bond pad (1142) may include a plurality of protrusions (1144) that define openings or voids (1146) configured to receive the teeth (1110), wherein the protrusions (1144) may be tapered, rounded, or otherwise configured to facilitate a self-alignment of each bond pad (1142) with a corresponding bond pad (1102). Metal bumps (e.g., gold stud bumps (1230)) may be applied to the bond pads (1222) that engage with the multi-material toothed bond pads (1202), wherein the multi-material toothed bond pads (1202) may be fully covered by an underfill region (1210), e.g., comprising epoxy.

9. 发明申请

WO2021173182A1 METAL-INSULATOR-METAL (MIM) CAPACITOR 审中-公开
公开(公告)号：WO2021173182A1
公开(公告)日：2021-09-02
申请号：PCT/US2020/047581
申请日：2020-08-24
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian
IPC分类号： H01L49/02 , H01L23/522
摘要： A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

10. 发明申请

WO2020146692A1 SYSTEM AND METHOD FOR MONITORING COPPER CORROSION IN AN INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：WO2020146692A1
公开(公告)日：2020-07-16
申请号：PCT/US2020/013006
申请日：2020-01-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： LENG, Yaojian
IPC分类号： H01L21/66 , G01N17/00
摘要： Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

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