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1. 发明申请

WO2010023615A1 COMPENSATION OF MOTION ARTIFACTS IN CAPACITIVE MEASUREMENT OF ELECTROPHYSIOLOGICAL SIGNALS 审中-公开
标题翻译：电生理信号电容测量中运动人物的补偿
公开(公告)号：WO2010023615A1
公开(公告)日：2010-03-04
申请号：PCT/IB2009/053715
申请日：2009-08-24
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , YIN, Bin , MEFTAH, Mohammed , IKKINK, Teunis, J.
发明人： YIN, Bin , MEFTAH, Mohammed , IKKINK, Teunis, J.
IPC分类号： A61B5/0408 , A61B5/0478
CPC分类号： A61B5/04284 , A61B5/04085 , A61B5/7214
摘要： The invention relates to a system and a method in which an electrophysiological signal is sensed capacitively with at least two closely spaced electrodes such that the electrodes experience strongly correlated skin-electrode distance variations. To be able to derive a motion artifact signal, the capacitive coupling between the electrodes and skin is made intentionally different. With a signal processing means the motion artifact signal can be removed from the measured signal to leave only the desired electrophysiological signal. Since the measured quantity is dependant on the electrode-skin distance itself, the system and method do not need to rely on the constancy of a transfer function. Hereby, they give reliable motion artifact free output signals.
摘要翻译：本发明涉及一种系统和方法，其中用至少两个紧密间隔的电极电容地感测电生理信号，使得电极经历强相关的皮肤电极距离变化。为了能够导出运动假象信号，电极和皮肤之间的电容耦合被有意地不同。利用信号处理装置，可以从测量的信号中去除运动假象信号，仅留下所需的电生理信号。由于测量的量取决于电极 - 皮肤距离本身，所以系统和方法不需要依赖传递函数的恒定性。因此，它们给出可靠的运动伪影输出信号。

2. 发明申请

WO2006051455A1 MEMORY INTEGRATED CIRCUIT 审中-公开
标题翻译：内存集成电路
公开(公告)号：WO2006051455A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053604
申请日：2005-11-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1036 , G11C7/1063 , G11C11/56
摘要： A memory integrated circuit contains a sensing circuit (12) that receives signals from addressed memory cells. The sensing circuit determines in which of a number of ranges the signals fall, the number of ranges being greater than the number values to which the cells can be programmed. An output circuit is provided that is arranged to supply either only data words that have been inferred from the detection, or also further information that provides more information about the ranges that have been detected than the data words only. Dependent on a control signal from external terminals of the memory integrated circuit the output circuit supplies the data words only to the external terminals or also the further information about the detected ranges in addition to the data words.
摘要翻译：存储器集成电路包含从寻址的存储器单元接收信号的感测电路（12）。感测电路确定信号下降的范围中的哪一个，范围的数量大于可以编程单元的数字值。提供了一种输出电路，其被布置为仅提供从检测中推断出的数据字，或者还提供了与仅数据字相比已经被检测的范围的更多信息的其他信息。取决于来自存储器集成电路的外部端子的控制信号，输出电路仅将数据字提供给外部端子，或者除了数据字之外还提供关于检测范围的进一步信息。

3. 发明申请

WO2006126117A3 SYSTEM COMPRISING A GENERATING DEVICE AND A COMPARING DEVICE 审中-公开
公开(公告)号：WO2006126117A3
公开(公告)日：2006-11-30
申请号：PCT/IB2006/051454
申请日：2006-05-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BOEVE, Hans, M., B. , IKKINK, Teunis, J. , VAN ACHT, Victor, M., G.
发明人： BOEVE, Hans, M., B. , IKKINK, Teunis, J. , VAN ACHT, Victor, M., G.
IPC分类号： G05D1/02
摘要： Systems (1) comprising generating devices (2) comprising sensors (21) for generating sensor signals representing orientations of the generating devices (2) are provided with comparing devices (3) comprising comparators (31) for comparing the sensor signals with reference signals for interpreting the orientations, to increase the number of possible applications. The generating devices (2) and the comparing devices (3) may form parts of one apparatus (4) or of different apparatuses and then communicate wiredly or wirelessly via radio or infrared. Reference sensors (33,52) for generating the reference signals and/or reference memories (34,53) for storing the reference signals may be located in the comparing devices (3) and/or in sources (5) and then communicate wiredly or wirelessly via radio or infrared. Further comparators (36) in the comparing devices (3) may introduce adjustable sensitivities.

4. 发明申请

WO2006095278A1 DRIVING OF A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：驱动电阻滞后元件的记忆矩阵
公开(公告)号：WO2006095278A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050617
申请日：2006-02-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读取极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

5. 发明申请

WO2006117727A1 A DEVICE COMPRISING A SENSOR MODULE 审中-公开
标题翻译：包含传感器模块的设备
公开(公告)号：WO2006117727A1
公开(公告)日：2006-11-09
申请号：PCT/IB2006/051313
申请日：2006-04-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BOEVE, Hans, M, B. , IKKINK, Teunis, J. , VAN VEEN, Nicolaas, J., A.
发明人： BOEVE, Hans, M, B. , IKKINK, Teunis, J. , VAN VEEN, Nicolaas, J., A.
IPC分类号： H01L27/146 , H01L31/0203
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： A device (1) comprising a sensor module (2) with a package (3) is produced at reduced costs by providing the package (3) with two or more substrates (4,5) each with a functional layer (14,15), at least one sensor (24,25) such as a magnetometer and/or an accelerometer being located in at least one functional layer (14,15), and by providing the package (3) with a system comprising solder bumps (7-12) for aligning the functional layers (14,15). The system either comprises a first number of solder bumps (7,8) for coupling the functional layers (14,15) electrically and mechanically to each other via first bonding elements (31) or comprises a third substrate (6) with a third functional layer (16) and a second number of solder bumps (9,10) for coupling the first and third functional layers (14,16) electrically and mechanically to each other via second bonding elements (32) and a third number of solder bumps (11,12) for coupling the second and third functional layers (15,16) electrically and mechanically to each other via third bonding elements (33). Mechanically and/or electrically dummy solder bumps improve the alignment of the functional layers (14,15).
摘要翻译：通过为封装（3）提供两个或多个具有功能层（14,15）的基板（4,5），以降低的成本制造包括具有封装（3）的传感器模块（2）的装置（1）至少一个传感器（24,25），例如磁力计和/或加速度计位于至少一个功能层（14,15）中，并且通过为包装（3）提供包括焊料凸块（7- 12），用于对准功能层（14,15）。该系统还包括第一数量的焊料凸块（7,8），用于通过第一接合元件（31）将功能层（14,15）电和机械地彼此耦合，或包括具有第三功能层层（16）和第二数量的焊料凸块（9,10），用于经由第二接合元件（32）和第三数量的焊料凸块（32）将第一和第三功能层（14,16）电和机械地彼此耦合 11,12），用于经由第三接合元件（33）将第二和第三功能层（15,16）电和机械地彼此耦合。机械和/或电虚拟焊料凸起改善了功能层（14,15）的对准。

6. 发明申请

WO2005124787A3 ELECTRICAL DEVICE HAVING A PROGRAMMABLE RESISTOR CONNECTED IN SERIES TO A PUNCH-THROUGH DIODE AND METHOD OF MANUFACTURING THEREFOR 审中-公开
公开(公告)号：WO2005124787A3
公开(公告)日：2005-12-29
申请号：PCT/IB2005/051893
申请日：2005-06-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
摘要： The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S). The invention also relates to a method of manufacturing such an electrical device. The method comprises the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material.

7. 发明申请

WO2006117728A1 DEVICE COMPRISING A SENSOR ARRANGEMENT AND AN UPDATER 审中-公开
标题翻译：包含传感器布置的装置和更新装置
公开(公告)号：WO2006117728A1
公开(公告)日：2006-11-09
申请号：PCT/IB2006/051314
申请日：2006-04-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , BOEVE, Hans, M., B. , VAN DE WALLE, Gerjan
发明人： IKKINK, Teunis, J. , BOEVE, Hans, M., B. , VAN DE WALLE, Gerjan
IPC分类号： G01C17/38 , G01C21/08
CPC分类号： G01C17/38
摘要： Devices (1) comprising sensor arrangements (2) for providing first field information (11-13) defining at least parts of first fields and for providing second field information (14, 15) defining at least parts of second fields are provided with updaters (4) for updating parameters of the first and/or second fields via criterion-dependent iterations, to become more reliable and user friendly. The fields may be earth gravitational fields and/or earth magnetic fields and/or further fields. The parameters comprise magnitudes of the fields and dot products of the fields. The criterion-dependent iterations comprise magnitude functions and dot product functions. The magnitude functions define new magnitudes being functions of old magnitudes and of updated magnitudes and the dot product functions define new dot products being functions of old dot products and of updated dot products . The criterion-dependent iterations further comprise one dimensional criteria and/or rectangular, hyperbolic and/or topped-off hyperbolic two dimensional criteria all defining threshold values.
摘要翻译：设备（1）包括用于提供限定第一场的至少一部分的第一场信息（11-13）和用于提供限定第二场的至少一部分的第二场信息（14,15）的传感器装置（2），其具有更新 4）用于通过基于标准的迭代来更新第一和/或第二场的参数，以变得更可靠和用户友好。场可以是地球引力场和/或地球磁场和/或其它场。参数包括字段的大小和字段的点积。标准依赖迭代包括大小函数和点积函数。幅度函数定义了新的幅度，它是旧幅度和更新幅度的函数，点积函数定义了新的点产品，它是旧点产品和更新的点产品的功能。依赖于标准的迭代还包括所有定义阈值的一维标准和/或矩形，双曲和/或顶点双曲线二维标准。

8. 发明申请

WO2005104132A1 ELECTRONIC CIRCUIT WITH MEMORY FOR WHICH A THRESHOLD LEVEL IS SELECTED 审中-公开
标题翻译：具有选择阈值级别的存储器的电子电路
公开(公告)号：WO2005104132A1
公开(公告)日：2005-11-03
申请号：PCT/IB2005/051305
申请日：2005-04-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J. , STEK, Aalbert , BOEVE, Hans, M., B.. , PHILLIPS, Gavin, N.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J. , STEK, Aalbert , BOEVE, Hans, M., B.. , PHILLIPS, Gavin, N.
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

9. 发明申请

WO2006117731A1 DEVICE COMPRISING A SENSOR ARRANGEMENT AND AN ESTIMATOR 审中-公开
标题翻译：包含传感器布置的设备和估计器
公开(公告)号：WO2006117731A1
公开(公告)日：2006-11-09
申请号：PCT/IB2006/051317
申请日：2006-04-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , BOEVE, Hans, M., B. , VAN DE WALLE, Gerjan
发明人： IKKINK, Teunis, J. , BOEVE, Hans, M., B. , VAN DE WALLE, Gerjan
IPC分类号： G01C17/38
CPC分类号： G01C17/38
摘要： Devices (1) comprising sensor arrangements (2) for providing first field information defining at least parts of first fields and for providing second field information defining first parts of second fields are provided with estimators (4) for estimating second parts of the second fields as functions of mixtures of the first and second field information, to become more reliable and user friendly. The fields may be earth gravitational fields and/or earth magnetic fields and/or further fields. The mixtures comprise dot products of the first and second fields and/or first products of first components of the first and second fields in first directions and/or second products of second components of the first and second fields in second directions. The second parts of the second field comprise third components of the second field in third directions. The estimators (4) can further estimate third components of the first field in third directions as further functions of the first field information.
摘要翻译：设置有用于提供定义第一场的至少一部分的第一场信息和用于提供定义第二场的第一部分的第二场信息的传感器装置（2），用于将第二场的第二部分估计为第一和第二场信息的混合功能变得更加可靠和用户友好。场可以是地球引力场和/或地球磁场和/或其它场。混合物包括第一和第二场中的第一和第二场的第一和第二场的第一组分和/或第二方向上的第一和第二场的第二组分的第二组分的第一产物和/或第一组分的第一产物的第一产物。第二场的第二部分包括在第三方向上的第二场的第三分量。估计器（4）可以进一步估计第三方向的第一场的第三分量作为第一场信息的另外的功能。

10. 发明申请

WO2006095295A1 CONTROL OF A MEMORY MATRIX WITH RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：具有电阻HYSTERESIS元件的记忆矩阵的控制
公开(公告)号：WO2006095295A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050672
申请日：2006-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second . During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12) , without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间来自第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）来回切换到全列更新状态在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

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