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    • 2. 发明申请
    • TRENCH-GATE SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE
    • TRENCH-GATE半导体器件及其制造
    • WO2002089195A2
    • 2002-11-07
    • PCT/IB2002/001375
    • 2002-04-25
    • KONINKLIJKE PHILIPS ELECTRONICS N.V.
    • PEAKE, Steven, T.PETKOS, GeorgiosFARR, Robert, J.ROGERS, Christopher, M.GROVER, Raymond, J.FORBES, Peter
    • H01L21/336
    • H01L29/7813H01L29/0696H01L29/41766H01L29/42368H01L29/6634H01L29/66348H01L29/66727H01L29/66848
    • Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4') with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11). Furthermore, implantation of the source region (13) is facilitated, and a channel-accommodating region (15) can also be provided using a high energy implant (61) after providing the insulating overlayer (18).
    • 紧凑型沟槽栅极半导体器件(例如具有亚微米间距(Yc)的蜂窝功率MOSFET)以具有以不同方式使用侧壁间隔物(52)的自对准技术制造。 沟槽栅极(11)容纳在窄沟槽(20)中,所述窄沟槽(20)经由位于掩模(51)的较宽窗口(51a)的侧壁处的间隔物(52)限定的窄窗口(52b)被蚀刻 身体表面(10a)。 间隔物(52)允许与沟槽栅极(11)相邻的源极区域(13)和沟槽栅极(11)之上的绝缘覆盖层(18)与该窄沟槽(20)自对准。 限定用于源极(33)的接触窗(18a)的覆盖层(18)在去除间隔物(52)之后以简单但可重复的方式通过沉积和回蚀来提供。 其与体表面(10a)的重叠(y4,y4')是明确的,因此降低了源电极(33)和沟槽栅极(11)之间的短路风险。 此外,源区域(13)的植入便利,并且在提供绝缘覆层(18)之后,也可以使用高能量注入(61)来提供沟道容纳区域(15)。