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1. 发明申请

WO1996023396A1 STACKABLE MODULES AND MULTIMODULAR ASSEMBLIES 审中-公开
标题翻译：可堆叠模块和多模组件
公开(公告)号：WO1996023396A1
公开(公告)日：1996-08-01
申请号：PCT/US1996000746
申请日：1996-01-22
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , CARSON, John, C. , DeCARO, Robert, E. , HSU, Ying
IPC分类号： H05K07/00
CPC分类号： H05K7/023 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/32225 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/49112 , H01L2224/49113 , H01L2224/49171 , H01L2224/4943 , H01L2224/73265 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/1517 , H01L2924/16152 , H01L2924/1627 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01R12/523 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Stacked multimodular circuit assemblies (10, 12, 14) are provided which comprise stacked, sealable, modules containing electronic circuitry (50), each module having a plurality of electrically conductive, embedded through-vias (52, 53) between the upper and lower major surfaces thereof. The through-vias are contained within the module matrix outside of the circuit-containing cavity or "tub" (55) of the module and within the outer edges of the module body. Electronic circuitry contained in the module cavity is electrically connected to the through-vias by signal traces or vias passing out of the cavity and into contact with the through-vias, and adjacent modules are electrically interconnected by sealable, multichannel connector array (90) between adjacent modules having electrically conductive channels (92) coupling opposing through-vias of the adjacent modules. The connector arrays can also serve to seal the assembly when the entire assemblage of modules is copressed and to connect the stacked modular assembly to exterior circuitry such as a printed circuit board or other devices. Methods are also provided for assembling and electrically interconnecting electronic components within such stacked multimodular assemblies by attaching components of an electronic circuit to at least two stackable modules of the type described within the cavity thereof, interconnecting the circuit components with the described through-vias, and stacking and interconnecting the stackable modules with the described multichannel connector arrays interposed between each adjacent module pair.
摘要翻译：提供堆叠的多模电路组件（10,12,14），其包括堆叠的可密封的包含电子电路（50）的模块，每个模块在上下之间具有多个导电的嵌入通孔（52,53）主要表面。通孔包含在模块矩阵外部的模块的电路容纳腔或“桶”（55）外部并且在模块体的外边缘内。包含在模块腔中的电子电路通过从腔体通过并与通孔接触的信号迹线或通孔与通孔电连接，并且相邻的模块通过可密封的多通道连接器阵列（90）电连接在相邻模块具有耦合相邻模块的相对通孔的导电通道（92）。连接器阵列还可用于在整个模块组合受到压制时将组件密封并将堆叠的模块化组件连接到诸如印刷电路板或其他装置的外部电路。还提供了用于通过将电子电路的组件附接到在其空腔内描述的类型的至少两个可堆叠模块来将电路部件与所描述的通孔相互连接的方式来组装和电连接在这种堆叠的多模组件内的电子部件，以及堆叠和互连可堆叠模块与介于每个相邻模块对之间的所述多通道连接器阵列。

2. 发明申请

WO1994026083A1 ELECTRONIC MODULE COMPRISING A STACK OF IC CHIPS 审中-公开
标题翻译：包含IC芯片堆栈的电子模块
公开(公告)号：WO1994026083A1
公开(公告)日：1994-11-10
申请号：PCT/US1994004322
申请日：1994-04-19
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , CARSON, John, C. , SOME, Raphael, R.
IPC分类号： H05K07/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06596 , H01L2924/10253 , H01L2924/00
摘要： An electronic module comprising a multiplicity of pre-stacked IC chips (30), such as memory chips, and an IC chip (34), referred to as an active substrate or active backplane, to which the access plane is directly secured. A multiplicity of aligned solder bumps (44) may interconnect the stack (32) and the substrate (34), providing electrical, mechanical and thermal interconnection. The active substrate is a silicon layer containing substantial amounts of integrated circuitry, which interfaces, on one side, with the integrated circuitry in the stacked chips, and, on the other side, with the external computer bus system. Some of the high priority circuitry which may be included in the substrate is used for control, fault-tolerance, buffering, and data management.
摘要翻译：包括多个预先堆叠的IC芯片（30）（诸如存储芯片）和被称为有源基板或有源背板的IC芯片（34）的电子模块，直接固定存取平面。多个对准的焊料凸块（44）可以互连堆叠（32）和基板（34），从而提供电气，机械和热互连。有源衬底是包含大量集成电路的硅层，其集成电路一侧与堆叠芯片中的集成电路接口，另一方面与外部计算机总线系统接口。可以包括在衬底中的一些高优先级电路用于控制，容错，缓冲和数据管理。

3. 发明申请

WO1989004113A1 HIGH-DENSITY ELECTRONIC MODULES, PROCESS AND PRODUCT 审中-公开
标题翻译：高密度电子模块，工艺和产品
公开(公告)号：WO1989004113A1
公开(公告)日：1989-05-05
申请号：PCT/US1987002746
申请日：1987-10-20
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , GO, Tiong, C.
IPC分类号： H05K07/10
CPC分类号： H05K7/023
摘要： A high-density electronic module (24) is disclosed, which is suitable for use as a DRAM, SRAM, ROM, logic unit, arithmetic unit, etc. It is formed by stacking integrated-circuit chips (22), each of which carries integrated circuitry. The chips are glued together, with their leads along one edge, so that all the leads of the stack are exposed on an access plane (28). Where heat extraction augmentation is needed, additional interleaved layers are included in the stacks which have high thermal conductivity, and are electrical insulators. These interleaved layers may carry rerouting electrical conductors. Bonding bumps (31 and 34) are formed at appropriate points on the access plane. A supporting substrate (26), formed of light transparent material, such as silicon, is provided with suitable circuitry and bonding bumps (38 and 42) on its face. A layer of insulation is applied to either the access plane or substrate face, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied. The substrate face is placed on the access plane of the stack, their bonding bumps are microscopically aligned, and then bonded together under heat and/or pressure. A layer of thermally conductive (but electrically non-conductive) adhesive material is inserted between the substrate and stack. The substrate and stack combination is then placed and wire bonded in a protective container having leads extending therethrough for external connection.
摘要翻译：公开了一种适用于DRAM，SRAM，ROM，逻辑单元，运算单元等的高密度电子模块（24）。它集成了集成电路芯片（22），每个集成电路芯片集成电路。芯片被胶合在一起，其引线沿着一个边缘，使得堆叠的所有引线暴露在访问平面（28）上。在需要增加热量的情况下，在具有高导热性的堆叠中包括额外的交错层，并且是电绝缘体。这些交错层可以承载重新路由的电导体。接合凸块（31和34）形成在接近平面上的适当点处。由诸如硅的透光材料形成的支撑衬底（26）在其表面上设置有合适的电路和接合凸块（38和42）。绝缘层被施加到接入面或衬底面，优选后者。在施加绝缘体之后，形成绝缘承载表面上的接合凸块。将基板面放置在堆叠的存取平面上，将它们的结合凸块微观对准，然后在加热和/或压力下粘合在一起。一层导热（但不导电）的粘合剂材料插入在基片和叠层之间。然后将衬底和堆叠组合放置并且线接合在具有延伸穿过其中的引线的保护容器中用于外部连接。

4. 发明申请

WO1988005251A1 HIGH DENSITY ELECTRONIC PACKAGE COMPRISING STACKED SUB-MODULES 审中-公开
标题翻译：包含堆叠子模块的高密度电子包装
公开(公告)号：WO1988005251A1
公开(公告)日：1988-07-14
申请号：PCT/US1988000060
申请日：1988-01-04
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , GO, Tiong, C.
IPC分类号： H05K03/36
CPC分类号： H01L23/5385 , H01L23/13 , H01L25/105 , H01L2225/107 , H01L2924/0002 , H01L2924/01004 , H01L2924/01014 , H01L2924/01079 , H01L2924/01322 , H01L2924/1627 , H01L2924/3011 , Y10T29/49126 , H01L2924/00
摘要： A high density electronic package (16) in which a stack of layer-like sub-modules have their edges (34) secured to a stack-carrying substrate (18), the latter being in a plane perpendicular to the planes in which the sub-modules extend. Each sub-module has a cavity (72), inside which one or more IC chips are located. Each cavity-providing sub-module may be formed either by securing a rectangular frame (32) to a chip-carrying substrate, or by etching a cavity in a single piece of material. In the latter case, the chips are mounted on the flat surface of one sub-module, and located inside the cavity of the next sub-module.

5. 发明申请

WO1986003338A1 APPARATUS AND METHOD FOR FABRICATING MODULES COMPRISING STACKED CIRCUIT-CARRYING LAYERS 审中-公开
标题翻译：用于制作包含堆叠电路层的模块的装置和方法
公开(公告)号：WO1986003338A1
公开(公告)日：1986-06-05
申请号：PCT/US1985002298
申请日：1985-11-20
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , BELANGER, Robert, J. , BISIGNANO, Alan, G.
IPC分类号： H01L21/70
CPC分类号： H01L21/67121 , H01L23/5385 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2924/0002 , H05K3/4611 , Y10T29/49126 , Y10T29/49133 , H01L2924/00
摘要： A method and related fixtures which permit formation of stacks of thin circuitry-carrying layers. The layers terminate in an access plane having a two-dimensional array of closely-spaced electrical leads. The method includes the steps of measuring the thickness of separate chips, selecting groups of chips having appropriate thicknesses, applying appropriate amounts of epoxy between adjacent chips, aligning the chips (and their electrical leads) in the direction parallel to their planes (i.e., the X-axis), and closing the cavity with an end wall which (a) exerts pressure on the stacked chips and epoxy in a direction perpendicular to the chip planes, and (b) establishes a fixed height of the stack in order to align the leads in the Y-axis. The final fixture provides a fixed-size cavity for confining the layers during curing of thermo-setting adhesive which has been applied between each adjacent pair of layers. An initial fixture is provided for accurately measuring the thickness of each layer under substantial layer-flattening pressure. An intermediate fixture is provided for wet stacking the layers prior to their insertion into the final fixture.

6. 发明申请

WO1995025341A1 3D STACK OF IC CHIPS HAVING LEADS REACHED BY VIAS THROUGH PASSIVATION COVERING ACCESS PLANE 审中-公开
标题翻译：由VIAS通过隐蔽覆盖访问平台获得的领先的IC芯片的3D堆叠
公开(公告)号：WO1995025341A1
公开(公告)日：1995-09-21
申请号：PCT/US1995002851
申请日：1995-03-07
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , JOHNSON, Tony, K.
IPC分类号： H01L21/58
CPC分类号： H01L25/50 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/0002 , H01L2924/00
摘要： A process (and resulting product) in which a plurality of IC chips (40, 42, 44) are stacked in a unitary structure having a novel method of exposing leads on the access plane (54) of the stack. After a layer of dielectric material (74) has been formed on the access plane, openings (preferably trenches) are formed, e.g., by wet lithographic processing, which expose the access plane leads (50, 52). Thereafter terminals (122) are formed on the access plane in contact with the leads. At the wafer level, layers of dielectric material (46, 48) are deposited which are sufficiently thick to permit the subsequent forming of openings in the access plane dielectric without uncovering any of the silicon of the IC chips.
摘要翻译：一种其中多个IC芯片（40,42,44）以单一结构堆叠的工艺（以及最终的产品），其具有在叠层的访问平面（54）上暴露引线的新方法。在接入平面上形成了一层电介质材料（74）之后，例如通过暴露出访问平面引线（50,52）的湿式平版印刷处理形成开口（优选是沟槽）。此后，在与引线接触的接入平面上形成端子（122）。在晶片级，沉积足够厚的介电材料层（46,48），以允许随后在存取平面电介质中形成开口，而不揭露IC芯片的任何硅。

7. 发明申请

WO1993000703A1 FABRICATING ELECTRONIC CIRCUITRY UNIT CONTAINING STACKED IC LAYERS HAVING LEAD REROUTING 审中-公开
标题翻译：制造电子电路单元包含堆积层叠层
公开(公告)号：WO1993000703A1
公开(公告)日：1993-01-07
申请号：PCT/US1992005348
申请日：1992-06-24
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , GO, Tiang, C. +di , MINIHAN, Joseph, A.
IPC分类号： H01L21/52
CPC分类号： H01L25/50 , H01L23/525 , H01L23/528 , H01L25/0657 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2225/06596 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A process and product are disclosed which apply advanced concepts of z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers (20), modification procedures are followed which create IC chips (38) having second level metal conductors (30) on top of passivation (52) (which covers the original silicon (48) and its aluminum or other metallization (44). The metal of the second level conductors (30) is different from and functions better for electrical conduction than the metallization included in the IC circuitry. The modified chips (38) are cut from the wafers (20), and then stacked to form multilayer IC devices (60). A stack has one or more access planes (64). After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads (92) are formed in contact with the terminals of the second level conductors (30) on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.
摘要翻译：公开了一种将先进技术应用于密集电子封装领域的工艺和产品。从含标准芯片的硅晶片（20）开始，按照修改步骤，其制造在钝化（52）（其覆盖原始硅（48）及其铝的顶部上具有第二级金属导体（30）的IC芯片（38）或其他金属化（44），所述第二电平导体（30）的金属与包括在所述IC电路中的金属化不同于并且具有更好的导电功能，所述改性芯片（38）从晶片（20）切割，然后堆叠以形成多层IC器件（60），堆叠具有一个或多个访问平面（64），堆叠之后，并且在接触平面上施加金属化之前，选择性蚀刻步骤去除可能的任何铝（或其他材料）金属端子焊盘（92）形成为与堆叠的芯片上的第二层导体（30）的端子接触，焊盘和端子由相同的金属材料按顺序形成以最大化T连接导通效率。

8. 发明申请

WO1986006214A1 THERMAL IMAGER INCORPORATING SENSOR WITHIN ELECTRONICS MODULE 审中-公开
标题翻译：热像仪在电子模块中配合传感器
公开(公告)号：WO1986006214A1
公开(公告)日：1986-10-23
申请号：PCT/US1986000688
申请日：1986-04-04
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , CARSON, John, C. , CLARK, Stewart, A.
IPC分类号： H01L27/14
CPC分类号： H04N5/33 , H01L27/14649 , H04N3/09
摘要： A thermal imaging system in which infrared radiation (56) from the viewed scene is transmitted to a two-dimensional detector array carried on the focal plane (52) of an optical/electronics module (54) which has embedded in it amplifying, filtering and multiplexing circuitry utilizing MOSFET transistors. The module is located inside the cooling device (62). Cooling requirements depend on the alternatives (a) of using detectors responsive to wavelengths in the 3.0 to 5.0 micron range, which require less cooling, or (b) of using detectors responsive to wavelengths in the 8.0 to 12.0 micron range, which require liquid nitrogen cooling. The two-dimensional detector array may be combined with a limited scanning, called ''nutation'', which causes each detector to view a plurality of pixels in the incoming infrared radiation.
摘要翻译：一种热成像系统，其中来自所观看场景的红外辐射（56）被传输到在嵌入其中的光/电子模块（54）的焦平面（52）上承载的二维检测器阵列放大，滤波和利用MOSFET晶体管的复用电路。模块位于冷却装置（62）的内部。冷却要求取决于使用响应于3.0至5.0微米范围波长的检测器的替代方案（a），其需要较少的冷却，或（b）使用响应于8.0至12.0微米范围内的波长的检测器，这些检测器需要液氮冷却。二维检测器阵列可以与受限扫描组合，称为“章动”，其使得每个检测器观察入射的红外辐射中的多个像素。

9. 发明申请

WO1985002283A1 DETECTOR ARRAY MODULE-STRUCTURE AND FABRICATION 审中-公开
标题翻译：检测器阵列模块和制造
公开(公告)号：WO1985002283A1
公开(公告)日：1985-05-23
申请号：PCT/US1983001750
申请日：1983-11-07
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , CARSON, John, C. , CLARK, Stewart, A.
IPC分类号： G06K09/28
CPC分类号： G01J1/4228 , G01J1/02 , G01J1/0209 , H01L25/042 , H01L25/0657 , H01L25/167 , H01L31/18 , H01L31/1804 , H01L2225/06524 , H01L2225/06551 , H01L2225/06555 , H01L2225/06579 , H01L2924/0002 , Y02E10/547 , Y02P70/521 , H01L2924/00
摘要： A photo-detector array module (12) which comprises a stack of semiconductor chips (14) having integrated circuitry on each chip. To permit the emplacement of photo-detectors (28) on the focal plane end (16), and of thin film circuitry (30) on the back plane end, each plane is etched to cut back the semiconductor material, then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.
摘要翻译：一种光电检测器阵列模块（12），其包括在每个芯片上具有集成电路的半导体芯片堆叠（14）。为了允许在焦平面端（16）上的光电检测器（28）和在背面端部上的薄膜电路（30）放置，每个平面被蚀刻以切割半导体材料，然后被钝化材料覆盖，然后研磨以揭开芯片上电引线的端部。

10. 发明申请

WO1997010657A1 SENSING AND SELECTING OBSERVED EVENTS FOR SIGNAL PROCESSING 审中-公开
标题翻译：感知和选择用于信号处理的观察事件
公开(公告)号：WO1997010657A1
公开(公告)日：1997-03-20
申请号：PCT/US1996014610
申请日：1996-09-11
申请人： IRVINE SENSORS CORPORATION
发明人： IRVINE SENSORS CORPORATION , SAUNDERS, Christ, H.
IPC分类号： H04J07/00
CPC分类号： G01D1/16
摘要： Circuitry for sensing a relatively large number of events, and outputting to processing circuitry only those events which have two characteristics: 1) a magnitude above a preselected threshold level (42); and 2) a rate of change greater than a preselected background rate of change. Logic circuitry (40) is used to assign any event which has the desired characteristics to an available output channel (24). Subtracter circuitry (34) causes the background to be subtracted from the sensing input (32), in order to limit the output (36) to non-background events.
摘要翻译：用于感测相对大量事件的电路，并且仅向具有两个特征的那些事件输出到处理电路：1）高于预先选择的阈值电平（42）的幅度; 和2）变化率大于预选的背景变化率。逻辑电路（40）用于将具有期望特性的任何事件分配给可用的输出通道（24）。减法器电路（34）使得从感测输入（32）中减去背景，以便将输出（36）限制为非背景事件。

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