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1. 发明申请

WO2010015678A2 IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：改善半导体器件中的焊接保护连接
公开(公告)号：WO2010015678A2
公开(公告)日：2010-02-11
申请号：PCT/EP2009/060213
申请日：2009-08-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , STAMPER, Anthony , ANDERSON, Felix, Patrick , MCDEVITT, Thomas, Leddy , EDELSTEIN, Daniel , COTE, William
发明人： STAMPER, Anthony , ANDERSON, Felix, Patrick , MCDEVITT, Thomas, Leddy , EDELSTEIN, Daniel , COTE, William
IPC分类号： H01L23/532 , H01L23/485 , H01L21/3105 , H01L21/768 , H01L21/60
CPC分类号： H01L24/13 , H01L21/3105 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L23/53238 , H01L23/53295 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2221/1036 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05647 , H01L2224/05666 , H01L2224/13022 , H01L2224/13027 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/45147 , H01L2224/48847 , H01L2924/00011 , H01L2924/01005 , H01L2924/01014 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2924/00 , H01L2924/01006
摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non- fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.
摘要翻译：具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。该结构包括在至少一部分没有氟边界层的电介质层中形成的沟槽。该结构还包括在沟槽中的铜线，其至少其底部与沟槽的非氟化物边界层接触。无铅焊料凸块与铜线电接触。

2. 发明申请

WO2004114396A1 INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：集成电路设备中的互连结构
公开(公告)号：WO2004114396A1
公开(公告)日：2004-12-29
申请号：PCT/EP2004/051131
申请日：2004-06-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , WILLE, William , EDELSTEIN, Daniel , COTE, William , BIOLSI, Peter , FRITCHE, John , UPHAM, Allan
发明人： WILLE, William , EDELSTEIN, Daniel , COTE, William , BIOLSI, Peter , FRITCHE, John , UPHAM, Allan
IPC分类号： H01L21/768
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76804
摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material (13), then the planarizing material (16) is deposited in the vias and on the dielectric material, and the barrier material (17) is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material (19), etched through the barrier material into the. planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.
摘要翻译：本发明涉及集成电路器件中的双镶嵌互连结构的制造。具体地，公开了一种利用平面化材料和扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。在该方法的优选双镶嵌实施例中，首先在电介质材料（13）中形成通孔，然后将平坦化材料（16）沉积在通孔和电介质材料上，并且阻挡材料（17）沉积在平坦化材料上。然后在成像材料（19）中光刻地形成沟槽，通过阻挡材料蚀刻进入。平坦化材料，并且沟槽图案被转移到电介质材料。在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。然后可以将所得的双镶嵌结构金属化。通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

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