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1. 发明申请

WO2013082030A1 DYNAMICALLY ENTERING LOW POWER STATES DURING ACTIVE WORKLOADS 审中-公开
标题翻译：动态工作期间动态进入低功率状态
公开(公告)号：WO2013082030A1
公开(公告)日：2013-06-06
申请号：PCT/US2012/066656
申请日：2012-11-27
申请人： INTEL CORPORATION , WANG, Ren , TAI, Tsung-Yuan C. , TSAI, JR-Shian , FLEMING, Bruce L. , MURALIDHAR, Rajeev D. , ERGIN, Mesut A. , IYER, Prakash N. , SESHADRI, Harinarayanan
发明人： WANG, Ren , TAI, Tsung-Yuan C. , TSAI, JR-Shian , FLEMING, Bruce L. , MURALIDHAR, Rajeev D. , ERGIN, Mesut A. , IYER, Prakash N. , SESHADRI, Harinarayanan
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.
摘要翻译：系统和方法可以提供用于识别与平台的活动工作负载相关联的运行时间信息，以及至少部分地基于运行时信息来为该平台进行主动空闲状态确定。此外，平台上的共享资源的低功率状态可以至少部分地基于主动空闲状态确定与主动工作负载的执行同时被控制。

2. 发明申请

WO2012087593A2 METHOD, APPARATUS AND SYSTEM TO TRANSITION SYSTEM POWER STATE OF A COMPUTER PLATFORM 审中-公开
标题翻译：计算机平台过渡系统功率状态的方法，装置和系统
公开(公告)号：WO2012087593A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063907
申请日：2011-12-08
申请人： INTEL CORPORATION , MURALIDHAR, Rajeev D. , SESHADRI, Harinarayanan , FLEMING, Bruce L. , RUDRAMUNI, Vishwesh M.
发明人： MURALIDHAR, Rajeev D. , SESHADRI, Harinarayanan , FLEMING, Bruce L. , RUDRAMUNI, Vishwesh M.
IPC分类号： G06F1/28 , G06F11/30 , G06F9/22
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3237 , G06F1/3268 , G06F1/3275 , G06F1/3278 , G06F11/3024 , G06F11/3055 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/154 , Y02D10/157
摘要： Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states.
摘要翻译：将平台上的处理器电源状态转换与平台上的另一个电源状态转换相结合的技术。在一个实施例中，操作系统的处理器调节器功能检测执行操作系统的处理器的空闲状态。基于处理器空闲条件和其他平台设备的一个或多个指示条件，绑定逻辑可以确定将平台转换到的系统功率状态。例如，绑定逻辑可以从多个空闲备用系统电源状态中的一个中选择。

3. 发明申请

WO2012087463A2 FRAMEWORK FOR RUNTIME POWER MONITORING AND MANAGEMENT 审中-公开
标题翻译：运行时间监控和管理框架
公开(公告)号：WO2012087463A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/061272
申请日：2011-11-17
申请人： INTEL CORPORATION , MURALIDHAR, Rajeev D. , SESHADRI, Harinarayanan , MAHALINGAM, Nithish , KADAM, Rushikesh S. , RUDRAMUNI, Vishwesh M. , THOMAS, Sujith
发明人： MURALIDHAR, Rajeev D. , SESHADRI, Harinarayanan , MAHALINGAM, Nithish , KADAM, Rushikesh S. , RUDRAMUNI, Vishwesh M. , THOMAS, Sujith
IPC分类号： G06F1/32 , G06F1/28 , G06F9/44
CPC分类号： G06F1/329 , G06F1/28 , G06F1/3206 , G06F9/5094 , Y02D10/24
摘要： Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.
摘要翻译：管理计算平台中的功率的系统和方法可以涉及监视平台中的多个硬件组件中的两个或更多个的运行时功耗以获得多个运行时功率确定。该方法还可以包括将多个运行时间功率确定中的一个或多个暴露给与平台相关联的操作系统。

4. 发明申请

WO2012054746A2 FINE GRAINED POWER MANAGEMENT IN VIRTUALIZED MOBILE PLATFORMS 审中-公开
标题翻译：虚拟移动平台中的细粒度电源管理
公开(公告)号：WO2012054746A2
公开(公告)日：2012-04-26
申请号：PCT/US2011/057128
申请日：2011-10-20
申请人： INTEL CORPORATION , MURALIDHAR, Rajeev, D. , RUDRAMUNI, Vishwesh, M. , SESHADRI, Harinarayanan , THOMAS, Sujith , KARUMURI, Srividya , KADAM, Rushikesh, S. , MAHALINGAM, Nithish
发明人： MURALIDHAR, Rajeev, D. , RUDRAMUNI, Vishwesh, M. , SESHADRI, Harinarayanan , THOMAS, Sujith , KARUMURI, Srividya , KADAM, Rushikesh, S. , MAHALINGAM, Nithish
IPC分类号： G06F9/44 , G06F9/22 , G06F1/26
CPC分类号： G06F1/3287 , G06F9/45533 , Y02D10/171 , Y02D50/20
摘要： A system and method of managing power may include determining a power state based on a first power management request from a first operating system executing on a mobile platform and a second power management request from a second operating system executing on the mobile platform. The first operating system and one or more components of the mobile platform can define a first virtual machine, and the second operating system and one or more components of the mobile platform can define a second virtual machine. In addition, the power state may be applied to the mobile platform.
摘要翻译：管理电力的系统和方法可以包括基于来自在移动平台上执行的第一操作系统的第一功率管理请求和来自在移动平台上执行的第二操作系统的第二功率管理请求来确定功率状态。移动平台的第一操作系统和一个或多个组件可以定义第一虚拟机，并且第二操作系统和移动平台的一个或多个组件可以定义第二虚拟机。此外，功率状态可以应用于移动平台。

5. 发明申请

WO2013169249A1 SCHEDULING TASKS AMONG PROCESSOR CORES 审中-公开
标题翻译：在处理器上调度任务
公开(公告)号：WO2013169249A1
公开(公告)日：2013-11-14
申请号：PCT/US2012/037171
申请日：2012-05-09
申请人： INTEL CORPORATION , SESHADRI, Harinarayanan , MURALIDHAR, Rajeev , RUDRAMUNI, Vishwesh M. , MANSOOR, Illyas
发明人： SESHADRI, Harinarayanan , MURALIDHAR, Rajeev , RUDRAMUNI, Vishwesh M. , MANSOOR, Illyas
IPC分类号： G06F9/46 , G06F15/80
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/00 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.
摘要翻译：本文描述了设备，计算机实现的方法，计算设备，系统和计算机可读介质（暂时性和非暂时性）的实施例，用于在多个处理器核之间调度多个任务。计算设备的多个处理器核心的第一处理器核心可以被转换到屏蔽状态，其中没有新的任务被分配给第一处理器核心，并且执行已经分配给第一处理器核心的任务来完成，以确定已经达到标准。在各种实施例中，标准可以基于计算设备的状况，例如计算设备可用的功率或与计算设备相关联的温度。在各种实施例中，在已经分配给第一处理器核心的任务执行完成之后，第一处理器核心可以转换到降低功率状态。

6. 发明申请

WO2013049371A2 CONSTRAINED BOOT TECHNIQUES IN MULTI-CORE PLATFORMS 审中-公开
标题翻译：多核平台中的约束引导技术
公开(公告)号：WO2013049371A2
公开(公告)日：2013-04-04
申请号：PCT/US2012/057597
申请日：2012-09-27
申请人： INTEL CORPORATION , MURALIDHAR, Rajeev , SESHADRI, Harinarayanan , RUDRAMUNI, Vishwesh, M.
发明人： MURALIDHAR, Rajeev , SESHADRI, Harinarayanan , RUDRAMUNI, Vishwesh, M.
CPC分类号： G06F1/3206 , G06F1/3287 , G06F9/4405 , Y02D10/171
摘要： Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that controls which specific core(s) are to be powered up/down and/or which power state these core(s) need to enter based, at least in part, on input from OS and/or software application(s). Other embodiments are also claimed and disclosed.
摘要翻译：描述了涉及多核平台中的受限引导技术的方法和装置。在一个实施例中，处理器可以包括至少部分地基于来自OS的输入来控制哪个或哪些特定内核将被加电/断电和/或这些内核需要输入哪个功率状态的逻辑，以及 /或软件应用程序。其他实施例也被要求并公开。

7. 发明申请

WO2012087566A2 METHOD, APPARATUS AND SYSTEM TO SAVE PROCESSOR STATE FOR EFFICIENT TRANSITION BETWEEN PROCESSOR POWER STATES 审中-公开
标题翻译：处理器状态用于处理器功率状态之间高效转换的方法，装置和系统
公开(公告)号：WO2012087566A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063485
申请日：2011-12-06
申请人： INTEL CORPORATION , MURALIDHAR, Rajeev , SESHADRI, Harinarayanan , FLEMING, Bruce , RUDRAMUNI, Vishwesh
发明人： MURALIDHAR, Rajeev , SESHADRI, Harinarayanan , FLEMING, Bruce , RUDRAMUNI, Vishwesh
IPC分类号： G06F9/22 , G06F9/44
CPC分类号： G06F1/3203 , G06F9/4418 , G06F9/463 , Y02D10/44
摘要： Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.
摘要翻译：提供用于实现处理器的功率状态转换的处理器状态的技术在一个实施例中，在处理器上执行的操作系统检测到将处理器转换到空闲处理器功率状态的机会。在特定实施例中，操作系统通过调用任务切换启动转换，其中描述处理器状态的信息被保存到任务切换段。

8. 发明申请

WO2019117961A1 POWER GOVERNANCE OF PROCESSING UNIT 审中-公开
公开(公告)号：WO2019117961A1
公开(公告)日：2019-06-20
申请号：PCT/US2017/066813
申请日：2017-12-15
申请人： INTEL CORPORATION
发明人： COOPER, Barnes , SESHADRI, Harinarayanan , MURALIDHAR, Rajeev , MUBEEN, Noor
IPC分类号： G06F1/32
摘要： Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

9. 发明申请

WO2017172027A1 SYSTEMS, METHODS AND DEVICES FOR DYNAMIC POWER MANAGEMENT OF DEVICES USING GAME THEORY 审中-公开
标题翻译：使用游戏理论的装置的动态电力管理系统，方法和装置
公开(公告)号：WO2017172027A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/015866
申请日：2017-01-31
申请人： INTEL CORPORATION
发明人： MURALIDHAR, Rajeev D. , SESHADRI, Harinarayanan
IPC分类号： G06F1/32
摘要： Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.
摘要翻译：集成设备的动态电源管理可以使用博弈论来实现。在一个示例中，各个设备（例如，CPU，GPU，通信等）的功率需求可以由管理员控制。引擎可以确定系统状况（例如，对接或未对接）并且使用奖励和/或惩罚矩阵来确定提供给调节器的功率设置。定期地，引擎可以重新评估调速器的系统状态和功率设置。例如，设备组件可以建模为游戏中的玩家。在闲置的电源管理情况下，玩家可以部署合作游戏策略以使系统处于低功耗状态。

10. 发明申请

WO2020205058A1 DETECTION OF KNOWN WORKLOAD PATTERNS 审中-公开
公开(公告)号：WO2020205058A1
公开(公告)日：2020-10-08
申请号：PCT/US2020/017277
申请日：2020-02-07
申请人： INTEL CORPORATION
发明人： BELAGAL MATH, Shravan Kumar , MUBEEN, Noor , SESHADRI, Harinarayanan
IPC分类号： G06F1/3203 , G06K9/62 , G06N20/00
摘要： Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

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