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1. 发明申请

WO2006072106A3 DEVICE AND METHOD FOR ON-DIE TEMPERATURE MEASUREMENT 审中-公开
公开(公告)号：WO2006072106A3
公开(公告)日：2006-07-06
申请号：PCT/US2005/047688
申请日：2005-12-29
申请人： INTEL CORPORATION , ROTEM, Efraim , HERMERDING, Jim , DISTEFANO, Eric , COOPER, Barnes
发明人： ROTEM, Efraim , HERMERDING, Jim , DISTEFANO, Eric , COOPER, Barnes
IPC分类号： G06F1/20
摘要： A system for measuring and managing thermal operations of a processor core on a semiconductor die using a sensor positioned in a hotspot of the processor core. A measured temperature reading is determined based upon a temperature sensed by the sensor. Interrupt signals and a software readable register indicating temperature information provide feedback about the thermal environment to the processor. Based upon the measured temperature reading, the interrupt signals direct the processor to modify operation.

2. 发明申请

WO2014209400A1 TECHNIQUES AND SYSTEM FOR MANAGING ACTIVITY IN MULTICOMPONENT PLATFORM 审中-公开
标题翻译：管理多机器平台活动的技术和系统
公开(公告)号：WO2014209400A1
公开(公告)日：2014-12-31
申请号：PCT/US2013/048778
申请日：2013-06-28
申请人： INTEL CORPORATION , DIEFENBAUGH, Paul S. , GORBATOV, Eugene , HENROID, Andrew , SAMSON, Eric C. , COOPER, Barnes
发明人： DIEFENBAUGH, Paul S. , GORBATOV, Eugene , HENROID, Andrew , SAMSON, Eric C. , COOPER, Barnes
IPC分类号： G06F1/26 , G06F9/38 , G06F9/46
CPC分类号： G06F1/3234 , G06F1/3246 , G06F1/3287 , G06F9/4893 , Y02D10/24 , Y02D50/20
摘要： In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
摘要翻译：在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。公开和要求保护其他实施例。

3. 发明申请

WO2013048523A1 FAST PLATFORM HIBERNATION AND RESUMPTION FOR COMPUTING SYSTEMS 审中-公开
标题翻译：计算系统的快速平台自适应和恢复
公开(公告)号：WO2013048523A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054473
申请日：2011-10-01
申请人： INTEL CORPORATION , COOPER, Barnes , SIDDIQI, Faraz, A.
发明人： COOPER, Barnes , SIDDIQI, Faraz, A.
IPC分类号： G06F9/06 , G06F9/22 , G06F1/32 , G06F12/00
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3275 , G06F3/0608 , G06F9/4418 , G06F12/023 , G06F13/00 , G06F21/81 , G06F2212/2022 , G06F2212/205 , G06F2212/401 , Y02D10/44
摘要： Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state upon receipt of a request, the transition to the first reduced power state including the processor to store context information for the computer in the volatile system memory. The apparatus further includes logic to transition the apparatus to a second reduced power state, the logic to copy the context data from the volatile system memory to the nonvolatile memory for the transition to the second reduced power state, where copying of the context data includes the logic to scan the volatile system memory to locate non- active memory elements in the volatile system memory, eliminate the non-active memory elements from the volatile system memory to generate compressed context data, and store the compressed context data in the nonvolatile memory.
摘要翻译：快速平台休眠和恢复计算系统。装置的实施例包括易失性系统存储器，非易失性存储器和根据操作系统操作的处理器，所述处理器在接收到请求时将装置转换到第一降低功率状态，转换到第一减少电源状态包括处理器，用于存储易失性系统存储器中的计算机的上下文信息。该装置还包括将装置转换到第二降低功率状态的逻辑，将上下文数据从易失性系统存储器复制到非易失性存储器以转换到第二降低功率状态的逻辑，其中上下文数据的复制包括用于扫描易失性系统存储器以定位易失性系统存储器中的非活动存储器元件的逻辑，从易失性系统存储器中消除非活动存储器元件以产生压缩上下文数据，并将压缩上下文数据存储在非易失性存储器中。

4. 发明申请

WO2006071661A1 AUDIO NOISE MITIGATION FOR POWER STATE TRANSITIONS 审中-公开
标题翻译：用于电力状态转换的音频噪声缓解
公开(公告)号：WO2006071661A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/046287
申请日：2005-12-20
申请人： INTEL CORPORATION , RODRIGUEZ, Jorge , CLINE, Leslie , COOPER, Barnes
发明人： RODRIGUEZ, Jorge , CLINE, Leslie , COOPER, Barnes
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.
摘要翻译：音频噪声缓解方法。一方面，提供与第一电源管理状态相关联的第一电压。接收响应于与至少第一类型的周期性退出事件相关联的指示的信号并且响应于该信号，开始向与第二状态相关联的第二电压的转变，到第二电压的转变的速率较慢而不是响应于非周期性退出事件而发起的类似电压转换。

5. 发明申请

WO2014105192A1 SYSTEM AND METHOD FOR CAUSING REDUCED POWER CONSUMPTION ASSOCIATED WITH THERMAL REMEDIATION 审中-公开
标题翻译：引起与热修复相关的减少功耗的系统和方法
公开(公告)号：WO2014105192A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048278
申请日：2013-06-27
申请人： INTEL CORPORATION , GOUGH, Robert , COOPER, Barnes , ASTEKAR, Basavaraj , GEDEON, Mazen , SOE, Soethiha
发明人： GOUGH, Robert , COOPER, Barnes , ASTEKAR, Basavaraj , GEDEON, Mazen , SOE, Soethiha
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3206 , G06F1/3243 , Y02D10/152 , Y02D10/16
摘要： Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.
摘要翻译：本文描述的特定实施例可以提供一种方法，其包括接收指示至少一个设备是否处于低功率模式的信号，至少部分地基于所述信号来确定所述至少一个设备处于第一热良性状态，以及执行与降低的热修复功率消耗相关联的第一操作。

6. 发明申请

WO2009085507A1 SYSTEM AND METHOD FOR FAST PLATFORM HIBERNATE AND RESUME 审中-公开
标题翻译：快速平台自由和恢复的系统和方法
公开(公告)号：WO2009085507A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/084710
申请日：2008-11-25
申请人： INTEL CORPORATION , COOPER, Barnes , SIDDIQI, Faraz A.
发明人： COOPER, Barnes , SIDDIQI, Faraz A.
IPC分类号： G06F13/10 , G06F12/00 , G06F9/46
CPC分类号： G06F1/3203
摘要： In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described.
摘要翻译：在一些实施例中，装置包括处理器核，更小的非易失性存储器，用于保存操作系统，程序和数据的更大的非易失性存储器以供处理器核心使用。该装置还包括作为用于处理器核的系统存储器的易失性存储器，以及功率管理逻辑以控制功率管理的至少一些方面。响应于电源状态改变命令，系统上下文存储在较小的非易失性存储器中，随后易失性存储器丢失电力，并且响应于恢复命令，易失性存储器接收电力并接收至少一部分系统上下文从较小的非易失性存储器。描述其他实施例。

7. 发明申请

WO2007078628A2 METHOD AND APPARATUS FOR PROVIDING FOR DETECTING PROCESSOR STATE TRANSITIONS 审中-公开
标题翻译：用于提供检测处理器状态转换的方法和装置
公开(公告)号：WO2007078628A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/047033
申请日：2006-12-08
申请人： INTEL CORPORATION , SRINIVASAN, Vasudevan , ARAI, Susumu , COOPER, Barnes
发明人： SRINIVASAN, Vasudevan , ARAI, Susumu , COOPER, Barnes
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/4818 , G06F11/3423 , G06F11/3466 , Y02D10/24
摘要： In some embodiments, the method and apparatus to provide for the detection of processor transition states is described. Some embodiments include at least two threads which provide detection for high and low priority states, which provide for power state transitions by the operating system: The low priority thread runs just prior to entry into an idle or low power state; the high priority thread runs when the idle state is ended or the highest power state is reached. In some embodiments, the use of these threads provides for the detection of processor state transitions and idle times independently of the operating system. Other embodiments are described.
摘要翻译：在一些实施例中，描述了提供用于检测处理器转换状态的方法和装置。一些实施例包括提供针对高优先级和低优先级状态的检测的至少两个线程，其提供操作系统的功率状态转换：低优先级线程在进入空闲或低功率状态之前运行; 高优先级线程在空闲状态结束或达到最高功率状态时运行。在一些实施例中，这些线程的使用提供独立于操作系统的处理器状态转换和空闲时间的检测。描述其他实施例。

8. 发明申请

WO2007002921A3 DISPLAY CONTROLLER 审中-公开
公开(公告)号：WO2007002921A3
公开(公告)日：2007-01-04
申请号：PCT/US2006/025774
申请日：2006-06-29
申请人： INTEL CORPORATION , KARDACH, James P. , WILLIAMS, David , BHOWMIK, Achintya K. , COOPER, Barnes
发明人： KARDACH, James P. , WILLIAMS, David , BHOWMIK, Achintya K. , COOPER, Barnes
IPC分类号： G09G3/20
摘要： Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.

9. 发明申请

WO2014210258A1 GENERIC HOST-BASED CONTROLLER LATENCY METHOD AND APPARATUS 审中-公开
标题翻译：一般基于主机的控制器延迟方法和装置
公开(公告)号：WO2014210258A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/044250
申请日：2014-06-26
申请人： INTEL CORPORATION , COOPER, Barnes
发明人： COOPER, Barnes
IPC分类号： G06F13/38 , G06F1/26 , G06F9/305 , G06F9/44
CPC分类号： G06F1/3268 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D10/154
摘要： Methods and apparatus relating to generic host-based controller latency are described. In one embodiment, latency information, corresponding to one or more devices, is detected from a host controller that controls access to the one or more devices. Detection of the latency information is performed in response to one or more transactions that are initiated by the host controller. Other embodiments are also claimed and disclosed.
摘要翻译：描述与通用的基于主机的控制器等待时间有关的方法和装置。在一个实施例中，从控制对一个或多个设备的访问的主机控制器检测对应于一个或多个设备的等待时间信息。响应于由主机控制器启动的一个或多个事务来执行等待时间信息的检测。还要求和公开其它实施例。

10. 发明申请

WO2014099288A1 SYSTEM AND METHOD FOR PROVIDING FOR POWER SAVINGS IN A PROCESSOR ENVIRONMENT 审中-公开
标题翻译：在处理器环境中提供节电的系统和方法
公开(公告)号：WO2014099288A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/071765
申请日：2013-11-25
申请人： INTEL CORPORATION , COOPER, Barnes , SIDDIQI, Faraz , PERRENOUD, Justin , SHE, Ping , OLSSON, Claes , BADRI, Assar , CLARK, Benjamin
发明人： COOPER, Barnes , SIDDIQI, Faraz , PERRENOUD, Justin , SHE, Ping , OLSSON, Claes , BADRI, Assar , CLARK, Benjamin
IPC分类号： G06F1/32
CPC分类号： G06F1/3268 , G06F1/3221 , Y02D10/154
摘要： Particular embodiments described herein can offer a method that includes receiving storage operation information that is to indicate one or more storage drive operations, receiving storage independent power information, determining, by a processor, a performance profile based at least in part on the storage operation information and the storage independent power information, and causing a setting of at least one power management directive that is to correspond with the performance profile.
摘要翻译：本文描述的特定实施例可以提供一种方法，其包括接收用于指示一个或多个存储驱动操作的存储操作信息，接收存储独立功率信息，至少部分地基于存储操作信息由处理器确定性能简档以及与存储无关的功率信息，并且使得至少一个与所述性能简档相对应的功率管理指令的设置。

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