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1. 发明申请

WO2015047334A1 ERROR CORRECTION IN NON_VOLATILE MEMORY 审中-公开
标题翻译： NON_VOLATILE MEMORY中的错误修正
公开(公告)号：WO2015047334A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062405
申请日：2013-09-27
申请人： INTEL CORPORATION , KWOK, Zion S. , MOTWANI, Ravi H. , PANGAL, Kiran , DAMLE, Prashant S.
发明人： KWOK, Zion S. , MOTWANI, Ravi H. , PANGAL, Kiran , DAMLE, Prashant S.
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/1068 , G06F11/10 , G06F11/1044 , G06F11/108 , G06F12/00 , G06F2212/7207 , G11C29/52 , H03M13/1515 , H03M13/152
摘要： Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.
摘要翻译：描述了存储器中用于纠错的装置，系统和方法。在一个实施例中，存储器控制器包括接收对存储在存储器中的数据的读取请求的逻辑，检索数据和至少一个相关联的纠错码字，其中数据和相关联的纠错码字分布在多个存储器件在存储器中，应用第一纠错程序来解码用数据检索的纠错码字，并响应错误校正码字中的不可校正错误，对存储器中的多个设备应用第二纠错例程。还公开并要求保护其他实施例。

2. 发明申请

WO2014051775A1 TECHNIQUES ASSOCIATED WITH PROTECTING SYSTEM CRITICAL DATA WRITTEN TO NON-VOLATILE MEMORY 审中-公开
标题翻译：与保护系统相关的技术关键数据写入非易失性存储器
公开(公告)号：WO2014051775A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047442
申请日：2013-06-24
申请人： INTEL CORPORATION , PANGAL, Kiran , MOTWANI, Ravi H. , DAMLE, Prashant S.
发明人： PANGAL, Kiran , MOTWANI, Ravi H. , DAMLE, Prashant S.
IPC分类号： G06F12/16 , G06F11/10 , G11C16/06
CPC分类号： G06F12/0246 , G06F11/1012 , G06F12/0238 , G06F2212/1032 , G06F2212/1041 , G06F2212/403 , G06F2212/7202 , G06F2212/7207 , G11C16/10 , G11C16/3459 , G11C16/349
摘要： Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed.
摘要翻译：公开了与保护写入非易失性存储器的系统关键数据相关的技术的示例。在一些示例中，可以使用第一数据保护方案将系统关键数据写入非易失性存储器。包括非系统关键数据的用户数据也可以使用第二数据保护方案写入非易失性存储器。对于这些示例，两个数据保护方案可以具有相同的给定数据格式大小。为使用第一数据保护方案提供了各种示例，该方案可以与使用第二数据保护方案提供给用户数据的保护相比提供对系统关键数据的增强保护。其他的例子被描述和要求保护。

3. 发明申请

WO2015080819A1 ERROR CORRECTION IN MEMORY 审中-公开
标题翻译：内存错误修正
公开(公告)号：WO2015080819A1
公开(公告)日：2015-06-04
申请号：PCT/US2014/061929
申请日：2014-10-23
申请人： INTEL CORPORATION , MOTWANI, Ravi H. , PANGAL, Kiran
发明人： MOTWANI, Ravi H. , PANGAL, Kiran
IPC分类号： G11C29/42 , G11C16/06
CPC分类号： G06F11/1008 , G06F11/10 , G06F11/1004 , G06F11/1048 , H03M13/05 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/2957
摘要： Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.
摘要翻译：描述了存储器中用于纠错的装置，系统和方法。在一个实施例中，控制器包括从主机设备接收存储在存储器中的数据的读取请求的逻辑，检索数据和相关联的纠错码字，将数据发送到主机设备，应用纠错例程来解码使用数据检索的纠错码字，并且响应于纠错码字中的错误，向主机设备发送与该错误相关联的数据的位置。还公开并要求保护其他实施例。

4. 发明申请

WO2015047239A1 MEMORY CONTROLLER WITH DISTRIBUTION TRANSFORMER 审中-公开
标题翻译：带分配变压器的内存控制器
公开(公告)号：WO2015047239A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061575
申请日：2013-09-25
申请人： INTEL CORPORATION , MOTWANI, Ravi H. , PANGAL, Kiran
发明人： MOTWANI, Ravi H. , PANGAL, Kiran
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F11/1012 , G06F13/16 , G06F13/1694 , G11C7/1006 , G11C13/0004 , G11C13/0069
摘要： Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m and n are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m':n' ratio for bits having the first logic value and bits having the second logic value, where m' and n' are real numbers that are different from one another and respectively differ from m and n. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.
摘要翻译：描述与存储器的存储器控制器相关的方法，装置和系统。在一个实施例中，存储器控制器可以包括被配置为接收要存储到存储器中的数据的分配变压器，其中所述数据具有用于具有第一逻辑值的位和具有第二逻辑值的位的m1：n1比的分布，其中 m和n是实数。分配变压器可以将数据变换为偏斜数据，其中偏斜数据对于具有第一逻辑值的位和具有第二逻辑值的位具有m'：n'比的分布，其中m'和n'是实数，分别不同于m和n。配电变压器可输出倾斜的数据以存储在存储器中。可以描述和要求保护其他实施例。

5. 发明申请

WO2015047228A1 USE OF ERROR CORRECTION POINTERS TO HANDLE ERRORS IN MEMORY 审中-公开
标题翻译：使用错误修正指针来处理存储器中的错误
公开(公告)号：WO2015047228A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061455
申请日：2013-09-24
申请人： INTEL CORPORATION , MOTWANI, Ravi H. , PANGAL, Kiran
发明人： MOTWANI, Ravi H. , PANGAL, Kiran
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/073 , G06F11/076 , G06F11/0772 , G06F11/1048
摘要： Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.
摘要翻译：这里描述了使用纠错指针（ECP）来处理存储器中的硬错误的方法，装置和系统。在实施例中，存储器控制器的读取模块可以读取存储在存储器中的码字。读取模块可以确定码字中的许多硬错误。响应于确定硬错误的数量超过阈值，读取模块可以存储与硬错误相关联的ECP信息。读取模块可以包括用于对码字执行ECC处理的纠错码（ECC）模块。读取模块可以使用ECP信息来解码码字以响应于ECC过程失败的确定来恢复数据。可以描述和要求保护其他实施例。

6. 发明申请

WO2013147775A1 RECONSTRUCTING CODEWORDS USING A SIDE CHANNEL 审中-公开
标题翻译：使用一个通道重新编码
公开(公告)号：WO2013147775A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031032
申请日：2012-03-28
申请人： INTEL CORPORATION , KALAVADE, Pranav , MOTWANI, Ravi H.
发明人： KALAVADE, Pranav , MOTWANI, Ravi H.
IPC分类号： H03M13/03
CPC分类号： G06F11/1412 , G06F11/1044 , G06F11/1402 , H03M13/1102 , H03M13/2906 , H03M13/2927
摘要： Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel. In various embodiments, a memory controller may be configured to determine that m of n die of non-volatile memory ("NVM") have failed iterative decoding. In various embodiments, the memory controller may be further configured to generate a side channel from n-m non-failed die and the m failed die other than a first failed die. In various embodiments, the memory controller may be further configured to reconstruct, using iterative decoding, a codeword stored on the first failed die of the m failed die based on the generated side channel and on soft input to an attempt to iteratively decode data stored on the first failed die. In various embodiments, the iterative decoding may include low-density parity-check decoding. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了使用侧信道对码字进行解码的设备，方法，计算机可读介质和系统配置。在各种实施例中，存储器控制器可以被配置为确定非易失性存储器（“NVM”）的n个管芯的m具有失败的迭代解码。在各种实施例中，存储器控制器还可以被配置为从n-m非故障芯片和除了第一故障芯片之外的m个故障模具产生侧通道。在各种实施例中，存储器控制器还可以被配置为基于生成的侧信道和软输入来重建使用迭代解码存储在m个失败管芯的第一个故障管芯上的代码字，以尝试迭代地解码存储在第一个失败的死亡在各种实施例中，迭代解码可以包括低密度奇偶校验解码。可以描述和/或要求保护其他实施例。

7. 发明申请

WO2013006579A2 NON-VOLATILE MEMORY ERROR MITIGATION 审中-公开
标题翻译：非易失性存储器错误缓解
公开(公告)号：WO2013006579A2
公开(公告)日：2013-01-10
申请号：PCT/US2012/045306
申请日：2012-07-02
申请人： INTEL CORPORATION , MOTWANI, Ravi H.
发明人： MOTWANI, Ravi H.
CPC分类号： G06F11/1048 , G06F11/073 , G06F11/076 , H03M13/1111
摘要： Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.
摘要翻译：用于解码非易失性存储器中的电平的技术。读取多位非易失性存储器中的单元的电平。使用最小的对数似然比（LLR）和修正的LLR来解码电平，其中修改的LLR是错位概率的函数。与解码电平对应的值被写入易失性存储器。

8. 发明申请

WO2013137851A1 DISTRIBUTED CODEWORD PORTIONS 审中-公开
标题翻译：分布式编码部分
公开(公告)号：WO2013137851A1
公开(公告)日：2013-09-19
申请号：PCT/US2012/028763
申请日：2012-03-12
申请人： INTEL CORPORATION , MOTWANI, Ravi H.
发明人： MOTWANI, Ravi H.
IPC分类号： G11C29/42 , G11C29/52 , G11C16/06 , G06F11/10
CPC分类号： H03M13/1105 , G06F11/1008 , G06F11/1048 , H03M13/1102
摘要： Embodiments of the present disclosure describe apparatus, methods, computer-readable media and system configurations for dividing error correcting code ("ECC") codewords into portions and storing the portions among multiple memory components. For example, a device may include non-volatile memory ("NVM") including m die. A memory controller may be configured to store portions of an ECC codeword among the m die. In various embodiments, a memory controller and/or an iterative decoder such as a low-density parity-check ("LDPC") decoder may be configured to decode ECC codewords based at least in part on reliability metrics associated with the m die. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于将纠错码（“ECC”）码字分成多个存储器组件并存储该部分的装置，方法，计算机可读介质和系统配置。例如，设备可以包括包括m个模块的非易失性存储器（“NVM”）。存储器控制器可以被配置为存储m个芯片中的ECC码字的部分。在各种实施例中，存储器控制器和/或诸如低密度奇偶校验（“LDPC”）解码器的迭代解码器可以被配置为至少部分地基于与m个模具相关联的可靠性度量来对ECC码字进行解码。可以描述和/或要求保护其他实施例。

9. 发明申请

WO2013006564A2 APPARATUS, SYSTEM, AND METHOD FOR GENERATING AND DECODING A LONGER LINEAR BLOCK CODEWORD USING A SHORTER BLOCK LENGTH 审中-公开
标题翻译：用于生成和解码使用短片块长度的较长线性块编码的装置，系统和方法
公开(公告)号：WO2013006564A2
公开(公告)日：2013-01-10
申请号：PCT/US2012/045284
申请日：2012-07-02
申请人： INTEL CORPORATION , MOTWANI, Ravi H.
发明人： MOTWANI, Ravi H.
CPC分类号： H03M13/1102 , H03M13/1105 , H03M13/1137 , H03M13/3707 , H03M13/3746 , H03M13/3761 , H03M13/3769
摘要： An apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length. The method comprises receiving data from a storage area and generating a codeword from the received data with an encoder, the codeword having a data portion and a parity portion, wherein the codeword has a first block length, and wherein the encoder applies a linear block code, the linear block code having a second block length that is shorter than the first block length.
摘要翻译：一种用于使用更短的块长度来生成和解码更长的线性块码字的装置，系统和方法。该方法包括：从存储区域接收数据，并用编码器从接收到的数据生成码字，码字具有数据部分和奇偶校验部分，其中码字具有第一块长度，并且其中编码器应用线性块码所述线性块码具有比所述第一块长度短的第二块长度。

10. 发明申请

WO2016160133A1 APPARATUS AND METHOD FOR DETECTING AND MITIGATING BIT-LINE OPENS IN FLASH MEMORY 审中-公开
标题翻译：用于检测和减轻闪存中的位线打开的装置和方法
公开(公告)号：WO2016160133A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/017228
申请日：2016-02-10
申请人： INTEL CORPORATION
发明人： MOTWANI, Ravi H. , KALAVADE, Pranav
IPC分类号： G11C16/08 , G11C16/34
CPC分类号： H03M13/1515 , G06F11/1012 , G06F11/1024 , G06F11/1068 , G11C7/1006 , G11C16/0483 , G11C29/025 , G11C29/42 , G11C29/52 , G11C2029/1204 , H03M13/1102
摘要： Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.
摘要翻译：描述了一种方法，其包括从非易失性存储器的一部分执行第一读取，第一读取以提供第一代码字; 解码第一码字; 确定解码操作是否失败; 当确定解码操作失败时，从非易失性存储器的一部分执行第二次读取，第二次读取以提供第二代码字; 以及用错误和擦除解码过程对第二码字进行解码。

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