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1. 发明申请

WO2011071594A2 ENERGY-EFFICIENT SET WRITE OF PHASE CHANGE MEMORY WITH SWITCH 审中-公开
标题翻译：具有开关功能的相变存储器的能量设置写
公开(公告)号：WO2011071594A2
公开(公告)日：2011-06-16
申请号：PCT/US2010/052833
申请日：2010-10-15
申请人： INTEL CORPORATION , KAU, Derchang , KALB, Johannes , KARPOV, Elijah , SPADINI, Gianpaolo
发明人： KAU, Derchang , KALB, Johannes , KARPOV, Elijah , SPADINI, Gianpaolo
IPC分类号： G11C13/02 , G11C16/34 , G11C16/10 , G11C16/26
CPC分类号： G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/008 , G11C2213/76
摘要： Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于具有开关的相变存储器的能量效率设置写入的装置和方法的实施例。可以描述和要求保护其他实施例。

2. 发明申请

WO2011059576A2 DOUBLE-PULSE WRITE FOR PHASE CHANGE MEMORY 审中-公开
标题翻译：双相脉冲写入相变存储器
公开(公告)号：WO2011059576A2
公开(公告)日：2011-05-19
申请号：PCT/US2010/050137
申请日：2010-09-24
申请人： INTEL CORPORATION , KAU, Derchang , KALB, Johannes , KLEHN, Brett
发明人： KAU, Derchang , KALB, Johannes , KLEHN, Brett
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0052 , G11C2013/008 , G11C2013/0092
摘要： The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step.
摘要翻译：本发明公开了一种方法，包括：利用第一步骤将相变材料从高RESET状态写入减弱的RESET状态; 用第二步将相变材料从减弱的RESET状态写入SET状态，第二步具有比第一步低的电流; 验证相变材料的参数，其中如果参数高于SET状态的目标，则重复第一步的写入，第二步的写入和验证，直到参数低于目标第一步的电流在每次迭代时递减一个递减量，而不低于第二步的电流。

3. 发明申请

WO2011084266A3 PROGRAMMING PHASE CHANGE MEMORIES USING OVONIC THRESHOLD SWITCHES 审中-公开
公开(公告)号：WO2011084266A3
公开(公告)日：2011-07-14
申请号：PCT/US2010/058233
申请日：2010-11-29
申请人： INTEL CORPORATION , LANGTRY, Timothy C. , DODGE, Richard , CASTRO, Hernan , KAU, Derchang , TANG, Stephan , HIRST, Jeremy
发明人： LANGTRY, Timothy C. , DODGE, Richard , CASTRO, Hernan , KAU, Derchang , TANG, Stephan , HIRST, Jeremy
IPC分类号： G11C13/02 , G11C16/34
摘要： A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state.

4. 发明申请

WO2012067871A2 PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY 审中-公开
标题翻译：用于存储器可扩展性能的管道结构
公开(公告)号：WO2012067871A2
公开(公告)日：2012-05-24
申请号：PCT/US2011/059529
申请日：2011-11-07
申请人： INTEL CORPORATION , SUNDARAM, Rajesh , KAU, Derchang , ZIMMERMAN, David J.
发明人： SUNDARAM, Rajesh , KAU, Derchang , ZIMMERMAN, David J.
IPC分类号： G11C13/02
CPC分类号： G11C13/0004 , G06F2213/0038 , G11C7/1039 , G11C13/0061 , G11C13/0069
摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
摘要翻译：提出了一种用于数据存储的设备。在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。

5. 发明申请

WO2018063728A1 SCALABLE BANDWIDTH NON-VOLATILE MEMORY 审中-公开
标题翻译：可扩展的带宽非易失性存储器
公开(公告)号：WO2018063728A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049502
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： SUNDARAM, Rajesh , FAZIO, Albert , KAU, Derchang , QAWAMI, Shekoufeh
IPC分类号： G06F13/16 , G11C13/00
摘要： Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
摘要翻译：公开并描述了交叉点存储器体系结构，设备，系统和方法，并且可以包括具有可扩展的增加的带宽的交叉点存储器核心子系统。存储器核心可以包括多个独立操作的分区，每个分区包括多个交叉点存储器阵列。

6. 发明申请

WO2017039982A1 THERMALLY REGULATED ELECTRONIC DEVICES, SYSTEMS, AND ASSOCIATED METHODS 审中-公开
标题翻译：热调节电子设备，系统和相关方法
公开(公告)号：WO2017039982A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/046196
申请日：2016-08-09
申请人： INTEL CORPORATION
发明人： KAU, Derchang
IPC分类号： H01L45/00 , H01L27/24 , H01L23/367 , H01L23/373
CPC分类号： H01L45/1293 , H01L23/3677 , H01L23/3735 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/144 , H01L45/16
摘要： Thermally-regulated electronic devices, structures, and systems having incorporated high thermal conductivity dielectric (HTCD) materials are disclosed and described, including associated methods.
摘要翻译：公开和描述了包括高导热介电（HTCD）材料的热调节电子器件，结构和系统，包括相关方法。

7. 发明申请

WO2015199829A1 REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY 审中-公开
标题翻译：跨点存储器中的参考架构
公开(公告)号：WO2015199829A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/030585
申请日：2015-05-13
申请人： INTEL CORPORATION
发明人： SRINIVASAN, Balaji , RIVERS, Doyle , KAU, Derchang , GOLDMAN, Matthew
IPC分类号： G11C13/02 , G11C7/10
CPC分类号： G11C13/0004 , G11C7/12 , G11C8/08 , G11C11/24 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0054 , G11C2013/0057 , G11C2213/77
摘要： The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V REF ) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on V REF and a detected memory cell voltage V LWL .
摘要翻译：本公开涉及交叉点存储器中的参考和感测架构。设备可以包括配置为选择用于存储器访问操作的目标存储器单元的存储器控制器。存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，其包括第一感测电路电容和第二感测电路电容，所述感测电路被配置为将所选择的GWL，LWL和第一感测电路电容预充电到WL偏置电压WLVDM，产生使用充电的参考电压（VREF）在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

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