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1. 发明申请

WO2006105543A2 TEMPERATURE DETERMINATION AND COMMUNICATION FOR MULTIPLE DEVICES OF A MEMORY MODULE 审中-公开
标题翻译：存储器模块的多个器件的温度测量和通信
公开(公告)号：WO2006105543A2
公开(公告)日：2006-10-05
申请号：PCT/US2006/012984
申请日：2006-03-30
申请人： INTEL CORPORATION , JAIN, Sandeep , WYATT, David , SHI, Jun , MISHRA, Animesh , HALBERT, John , ISBARA, Melik
发明人： JAIN, Sandeep , WYATT, David , SHI, Jun , MISHRA, Animesh , HALBERT, John , ISBARA, Melik
IPC分类号： G11C5/00 , G01K1/02 , G01K7/01 , G01K3/00 , G01K7/42 , G11C7/10
CPC分类号： G11C5/04 , G01K7/425 , G11C7/04 , G11C7/1048 , G11C7/1051 , G11C7/1063 , G11C11/40626 , G11C29/028 , G11C2029/5002
摘要： Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.
摘要翻译：在包含多个存储器件的存储器模块的上下文中描述了热管理和通信。在一个示例中，本发明包括确定第一存储器件的温度，第一存储器件包含多个存储器单元，在确定第一存储器件的温度之后确定第二存储器件的温度，第二存储器器件包含多个存储单元，并且基于第一和第二温度的评估来产生报警。在另一示例中，本发明包括检测包含多个存储器件的存储器模块的存储器件上的热事件，检测存储器模块的事件总线的状态，以及如果事件发生在事件总线上的警报公共汽车处于空闲状态。

2. 发明申请

WO2006069356A2 A METHOD, APPARATUS, AND SYSTEM FOR ACTIVE REFRESH MANAGEMENT 审中-公开
标题翻译：一种用于主动刷新管理的方法，装置和系统
公开(公告)号：WO2006069356A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/046943
申请日：2005-12-21
申请人： INTEL CORPORATION , JAIN, Sandeep , MISHRA, Animesh , HALBERT, John
发明人： JAIN, Sandeep , MISHRA, Animesh , HALBERT, John
IPC分类号： G11C11/406
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40618 , G11C11/40622
摘要： A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.
摘要翻译：一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数，从而减少刷新期间消耗的功率量。

3. 发明申请

WO2005050599A2 BUFFERED MEMORY MODULE WITH IMPLICIT TO EXPLICIT MEMORY COMMAND EXPANSION 审中-公开
标题翻译：缓冲存储器模块，不明显的存储器命令扩展
公开(公告)号：WO2005050599A2
公开(公告)日：2005-06-02
申请号：PCT/US2004/036964
申请日：2004-11-05
申请人： INTEL CORPORATION , HALBERT, John , FREEMAN, Chris , WILLIAMS, Michael , BAINS, Kiljit , ELLIS, Robert , VOGT, Pete
发明人： HALBERT, John , FREEMAN, Chris , WILLIAMS, Michael , BAINS, Kiljit , ELLIS, Robert , VOGT, Pete
IPC分类号： G09F13/00
CPC分类号： G06F13/16
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于缓冲存储器模块的方法和装置。在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作。例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质的存储器通道带宽。描述和要求保护其他实施例。

4. 发明申请

WO2009121022A3 SYSTEMS, METHODS, AND APPARATUSES TO SAVE MEMORY SELF-REFRESH POWER 审中-公开
公开(公告)号：WO2009121022A3
公开(公告)日：2009-10-01
申请号：PCT/US2009/038670
申请日：2009-03-27
申请人： INTEL CORPORATION , BAINS, Kuljit , HALBERT, John , WILLIAMS, Michael, W.
发明人： BAINS, Kuljit , HALBERT, John , WILLIAMS, Michael, W.
IPC分类号： G11C11/402 , G11C11/4078 , G11C11/4074 , G11C11/406 , G11C29/42
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.

5. 发明申请

WO2005066965A2 INTEGRAL MEMORY BUFFER AND SERIAL PRESENCE DETECT CAPABILITY FOR FULLY-BUFFERED MEMORY MODULES 审中-公开
标题翻译：整体内存缓冲区和完整存储器模块的串行存在检测能力
公开(公告)号：WO2005066965A2
公开(公告)日：2005-07-21
申请号：PCT/US2004/041901
申请日：2004-12-13
申请人： INTEL CORPORATION , HALBERT, John , FREEMAN, Chris , WILLIAMS, Michael , BAINS, Kuljit , ELLIS, Robert
发明人： HALBERT, John , FREEMAN, Chris , WILLIAMS, Michael , BAINS, Kuljit , ELLIS, Robert
IPC分类号： G11C5/00
CPC分类号： G11C7/1051 , G06F13/1673 , G06F13/1684 , G11C7/1078 , G11C7/20
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于缓冲存储器模块的方法和装置。在示例性系统中，串行存在检测功能被包括在存储器模块缓冲器内，而不是由安装在存储器模块上的单独的EEPROM器件提供。因此，各种实施例可以提供成本节省，芯片放置和信号路由简化，并且在某些情况下可以在模块上保存引脚。描述和要求保护其他实施例。

6. 发明申请

WO2013081634A1 STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS 审中-公开
标题翻译：具有接口的堆叠存储器提供偏移互连
公开(公告)号：WO2013081634A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/063191
申请日：2011-12-02
申请人： INTEL CORPORATION , VOGT, Pete , SCHAEFER, Andre , MORROW, Warren , HALBERT, John , KIM, Jin , SHOEMAKER, Kenneth
发明人： VOGT, Pete , SCHAEFER, Andre , MORROW, Warren , HALBERT, John , KIM, Jin , SHOEMAKER, Kenneth
IPC分类号： H01L27/10 , H01L27/108 , H01L21/8242
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/481 , H01L24/16 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
摘要： Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.
摘要翻译：用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

7. 发明申请

WO2010039625A2 COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE 审中-公开
标题翻译：用于可变设备宽度和可缩放预取和页面大小的通用存储器设备
公开(公告)号：WO2010039625A2
公开(公告)日：2010-04-08
申请号：PCT/US2009/058531
申请日：2009-09-28
申请人： INTEL CORPORATION , BAINS, Kuljit S. , HALBERT, John
发明人： BAINS, Kuljit S. , HALBERT, John
IPC分类号： G11C11/4093 , G11C11/4096 , G11C11/4063 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1021 , G11C7/1045 , G11C11/4096 , G11C2207/107 , G11C2207/108
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.
摘要翻译：本发明的实施例通常针对用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。在一些实施例中，公共存储器设备（诸如DRAM）可以以包括例如x4模式，x8模式和x16模式的多种模式中的任何模式进行操作。由DRAM提供的页面大小可以根据DRAM的模式而变化。在一些实施例中，由DRAM预取的数据量也取决于DRAM的模式而变化。

8. 发明申请

WO2018004830A1 MEMORY CONTROLLER-CONTROLLED REFRESH ABORT 审中-公开
标题翻译：内存控制器控制的刷新中止
公开(公告)号：WO2018004830A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/031620
申请日：2017-05-08
申请人： INTEL CORPORATION
发明人： QUERBACH, Bruce , BAINS, Kuljit , HALBERT, John
IPC分类号： G11C11/406 , G11C7/10 , G06F3/06
CPC分类号： G11C11/40618 , G06F3/0604 , G06F3/0632 , G06F3/0659 , G06F3/0679 , G11C11/40603 , G11C11/40611 , G11C11/40622 , G11C14/0009
摘要： A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.
摘要翻译：内存子系统启用刷新中止命令。内存控制器可以发送中断以发送到内存设备的进程内刷新命令。刷新中止使得存储器控制器能够在刷新命令引起多行存储器刷新的情况下更精确地控制由存储器设备执行的操作的定时。存储器控制器可以在存储器器件的有效操作期间发出刷新命令，这是当存储器器件控制刷新时的主动操作刷新，而不是自刷新。内存控制器可以在刷新期间以及刷新完成之前发出刷新中止。因此，存储器控制器对刷新开始以及存储器设备可用于访问时具有确定性控制。

9. 发明申请

WO2016048634A1 EXCHANGING ECC METADATA BETWEEN MEMORY AND HOST SYSTEM 审中-公开
标题翻译：存储器和主机系统之间交换ECC元数据
公开(公告)号：WO2016048634A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/048776
申请日：2015-09-08
申请人： INTEL CORPORATION
发明人： BONEN, Nadav , BAINS, Kuljit , HALBERT, John
IPC分类号： G06F11/10 , G06F12/00 , G06F13/16
CPC分类号： G06F11/1076 , G06F11/1004 , G06F11/1048
摘要： Exposing internal error correction bits from a memory device for use as metadata bits by an external memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device exposes the internal error correction bits to the memory controller to allow the memory controller to use the data.
摘要翻译：从存储器件中公开内部纠错位，用于由外部存储器控制器用作元数据位。在第一模式中，存储器件在存储器件处应用用于内部纠错的内部纠错位。在第二模式中，存储器件将内部纠错位公开到存储器控制器以允许存储器控制器使用数据。

10. 发明申请

WO2018063697A1 STAGGERING INITIATION OF REFRESH IN A GROUP OF MEMORY DEVICES 审中-公开
标题翻译：在一组存储设备中刷新刷新指令
公开(公告)号：WO2018063697A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049315
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： TOMISHIMA, Shigeki , HALBERT, John , BAINS, Kuljit
IPC分类号： G11C11/406 , G11C11/4076
摘要： Memory refresh includes timing offsets for different memory devices, to initiate refresh of different memory devices at different times. A memory controller sends a refresh command to cause refresh of multiple memory devices. In response to the refresh command, the multiple memory devices initiate refresh with timing offsets relative to another of the memory devices. The timing offsets reduce the instantaneous power surge associated with all memory devices starting refresh simultaneously.
摘要翻译：存储器刷新包括不同存储器设备的定时偏移，以在不同时间启动不同存储器设备的刷新。内存控制器发送刷新命令以引起多个内存设备的刷新。响应于刷新命令，多个存储器设备利用相对于另一个存储器设备的定时偏移来发起刷新。时序偏移减少了与所有存储器设备同时开始刷新相关的瞬时功率浪涌。

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