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1. 发明申请

WO2010117518A2 CONTROL OF ON-DIE SYSTEM FABRIC BLOCKS 审中-公开
标题翻译：控制面板系统织物块
公开(公告)号：WO2010117518A2
公开(公告)日：2010-10-14
申请号：PCT/US2010/026078
申请日：2010-03-03
申请人： INTEL CORPORATION , FANG, Zhen , WAGH, Mahesh , AJANOVIC, Jasmin , ESPIG, Michael, E. , IYER, Ravishankar
发明人： FANG, Zhen , WAGH, Mahesh , AJANOVIC, Jasmin , ESPIG, Michael, E. , IYER, Ravishankar
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08 , G06F15/16
CPC分类号： G06F12/1036 , G06F12/0292 , G06F12/0888 , G06F12/10 , G06F12/1027 , G06F2212/206
摘要： Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
摘要翻译：描述了用于控制片上系统结构（OSF）块的方法和装置。在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。还公开了其他实施例。

2. 发明申请

WO2009045884A2 ADDRESS TRANSLATION CACHING AND I/O CACHE PERFORMANCE IMPROVEMENT IN VIRTUALIZED ENVIRONMENTS 审中-公开
标题翻译：地址翻译缓存和虚拟化环境中的I / O高速缓存性能改进
公开(公告)号：WO2009045884A2
公开(公告)日：2009-04-09
申请号：PCT/US2008/077819
申请日：2008-09-26
申请人： INTEL CORPORATION , WAGH, Mahesh , AJANOVIC, Jasmin
发明人： WAGH, Mahesh , AJANOVIC, Jasmin
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/023 , G06F12/10 , G06F12/1009 , G06F12/1027 , G06F12/121 , G06F2212/152
摘要： Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.
摘要翻译：描述了在虚拟化环境中改进地址转换缓存和/或输入/输出（I / O）缓存性能的方法和装置。在一个实施例中，由端点设备提供的提示可用于更新存储在I / O高速缓存中的信息。这样的信息可以用于在实施例中实现更有效的替换策略。还公开了其他实施例。

3. 发明申请

WO2010129096A2 A PACKETIZED INTERFACE FOR COUPLING AGENTS 审中-公开
标题翻译：用于联接代理的封装接口
公开(公告)号：WO2010129096A2
公开(公告)日：2010-11-11
申请号：PCT/US2010/027604
申请日：2010-03-17
申请人： INTEL CORPORATION , WAGH, Mahesh , SINGHAL, Abhishek , AJANOVIC, Jasmin
发明人： WAGH, Mahesh , SINGHAL, Abhishek , AJANOVIC, Jasmin
IPC分类号： G06F13/42
CPC分类号： H04L69/22 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed
摘要翻译：在一个实施例中，本发明包括在第一半导体管芯上的结构，以根据片上协议与管芯上的至少一个代理进行通信，以及耦合到该结构的分组层，以从该结构接收命令和数据信息多个链路并且将信息分组成分组，以经由内部分组化链路从芯片传输到另一个管芯。描述和要求保护其他实施例

4. 发明申请

WO2014133527A1 LEVERAGING AN ENUMERATION AND/OR CONFIGURATION MECHANISM OF ONE INTERCONNECT PROTOCOL FOR A DIFFERENT INTERCONNECT PROTOCOL 审中-公开
标题翻译：针对不同互联协议的“互联互通协议”的引用和/或配置机制
公开(公告)号：WO2014133527A1
公开(公告)日：2014-09-04
申请号：PCT/US2013/028365
申请日：2013-02-28
申请人： INTEL CORPORATION , RANGANATHAN, Sridharan , WAGH, Mahesh
发明人： WAGH, Mahesh
IPC分类号： G06F13/14 , G06F13/42
CPC分类号： G06F13/42 , G06F3/0661 , G06F13/387 , G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.
摘要翻译：一方面的互连架构设备包括处理器，用于生成与LLI不同的互连协议的事务。互连架构设备还包括与处理器耦合的转换逻辑。转换逻辑是将与LLI不同的互连协议的事务转换为LLI数据包。互连架构设备还包括与转换逻辑耦合的LLI控制器。 LLI控制器将互连架构设备与LLI链路耦合。 LLI控制器将在LLI链路上发送LLI报文。

5. 发明申请

WO2009094339A3 ENABLING FLEXIBILITY OF PACKET LENGTH IN A COMMUNICATION PROTOCOL 审中-公开
公开(公告)号：WO2009094339A3
公开(公告)日：2009-07-30
申请号：PCT/US2009/031461
申请日：2009-01-20
申请人： INTEL CORPORATION , WAGH, Mahesh
发明人： WAGH, Mahesh
IPC分类号： G06F13/42 , G06F13/14 , H04L12/56
摘要： In one embodiment, the present invention includes a method for transmitting a packet from a transmitter to a receiver along an interconnect and terminating transmission of the packet at a packet disconnect boundary, which has a length less than a payload length of the packet. After such termination, another packet such as a higher priority packet can be transmitted, or a remainder of the original packet may be transmitted as a separate packet. Other embodiments are described and claimed.

6. 发明申请

WO2015099719A1 MULTICHIP PACKAGE LINK 审中-公开
标题翻译：多媒体包链接
公开(公告)号：WO2015099719A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077744
申请日：2013-12-26
申请人： INTEL CORPORATION , WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
发明人： WU, Zuoguo J. , WAGH, Mahesh , DAS SHARMA, Debendra , PASDAST, Gerald S. , AYYASAMY, Ananthan , LI, Xiaobei , BLANKENSHIP, Robert G. , SAFRANEK, Robert J.
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/4282 , G06F13/124 , G06F13/4273 , G06F15/173 , Y02D10/14 , Y02D10/151
摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
摘要翻译：提供物理层逻辑，其是在物理链路的一个或多个数据通道上接收数据，在物理链路的另一个通道上接收一个有效信号，该有效信号标识该有效数据将跟随有效信号在一个或更多的数据通道，并且在物理链路的另一个通道上接收标识在一个或多个数据通道上的数据类型的流信号。

7. 发明申请

WO2014004737A1 LOW POWER LOW FREQUENCY SQUELCH BREAK PROTOCOL 审中-公开
标题翻译：低功率低频率方案
公开(公告)号：WO2014004737A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/048000
申请日：2013-06-26
申请人： INTEL CORPORATION , WAGH, Mahesh
发明人： WAGH, Mahesh
IPC分类号： G06F13/14 , G06F13/42
CPC分类号： G06F1/3253 , G06F1/3209 , G06F13/4282 , G06F2213/0026 , Y02D10/151
摘要： Methods and apparatus for provision of a low power, low frequency squelch break protocol are described. In some embodiments, a fixed or variable time transmitter LFPS (Low Frequency Periodic Signaling) mechanism may be used that does not require a handshake and therefore much simpler in implementation than USB3 (Universal Serial Bus 3.0), for example. Also, an embodiment does not require a link common mode to be established and therefore may be optimized to support shorter durations for effecting exit from an electrical idle state that may be established via power-gating, for example. Other embodiments are also disclosed.
摘要翻译：描述了提供低功率，低频静噪中断协议的方法和装置。在一些实施例中，例如可以使用固定或可变时间发射机LFPS（低频周期性信令）机制，其不需要握手，因此比USB3（通用串行总线3.0）简单得多。而且，实施例不需要建立链路共同模式，因此可以被优化以支持更短的持续时间，以实现例如通过电源门控建立的电空闲状态的退出。还公开了其他实施例。

8. 发明申请

WO2022154831A1 LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0, CXL 3.0, AND UPI 3.0 PROTOCOLS 审中-公开
公开(公告)号：WO2022154831A1
公开(公告)日：2022-07-21
申请号：PCT/US2021/050772
申请日：2021-09-17
申请人： INTEL CORPORATION
发明人： CHOUDHARY, Swadesh , WAGH, Mahesh , DAS SHARMA, Debendra
IPC分类号： G06F13/38 , G06F13/40 , G06F11/10
摘要： In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

9. 发明申请

WO2018017208A1 TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON SET OF INTERCONNECT CONNECTORS 审中-公开
标题翻译：用于为一组相互连接的连接器支持多种互连协议的技术
公开(公告)号：WO2018017208A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/037408
申请日：2017-06-14
申请人： INTEL CORPORATION
发明人： WAGH, Mahesh , MYERS, Mark S. , VAN DOREN, Stephen R. , ZIAKAS, Dimitrios , COURY, Bassam
IPC分类号： G06F13/42
摘要： Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.
摘要翻译：实施例通常可以指向用于确定多个连接器的配置的设备，系统，方法和技术，该配置将第一互连协议与多个连接器的第一子集相关联，以及与所述多个连接器的第二子集的第二互连协议，所述第一互连协议和所述第二互连协议是不同的互连协议，并且每个互连协议包括串行链路协议，相干链路协议和加速器链路协议中的一个，引起处理用于根据第一互连协议经由多个连接器的第一子集进行通信的数据，并且根据第二互连协议引起用于经由多个连接器的第二子集进行通信的数据的处理。

10. 发明申请

WO2017052661A1 MULTICHIP PACKAGE LINK ERROR DETECTION 审中-公开
标题翻译：多媒体封装链路错误检测
公开(公告)号：WO2017052661A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052509
申请日：2015-09-26
申请人： INTEL CORPORATION
发明人： IYER, Venkatraman , BLANKENSHIP, Robert G. , WAGH, Mahesh , WU, Zuoguo
IPC分类号： H04L1/00 , H04L1/20 , H04L29/06
CPC分类号： G06F11/1004 , G06F13/16 , G06F2213/16 , H04L1/00 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0075 , H04L1/1607 , H04L1/20 , H04L29/06 , H04L2001/0094
摘要： First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
摘要翻译：在物理链路的多个数据通道上接收第一数据，并且在标识第一数据的类型的流道上接收与第一数据相对应的流信号。在第一数据中识别特定类型的错误检测码的第一实例。在多个数据通道的至少一部分上接收第二数据，并且在标识第二数据的类型的流线路上接收对应于第二数据的流信号。在第二数据中识别特定类型的错误检测码的第二实例。流道是物理链路的另一条通道，在某些情况下，第二数据的类型与第一数据的类型不同。

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