会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • BALANCED CONTROL OF PROCESSOR TEMPERATURE
    • 加工温度平衡控制
    • WO2016025095A1
    • 2016-02-18
    • PCT/US2015/038125
    • 2015-06-26
    • INTEL CORPORATION
    • ROSENZWEIG, NirRAJWAN,, DoronSHAPIRA, DoritSHULMAN, NadavZIV, Tomer
    • G06F1/26G06F1/32G06F1/20
    • G06F1/206G01K1/026G01K13/00G06F1/3206G06F1/3234G06F1/324
    • In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
    • 在一个实施例中,处理器包括多个核心和多个温度传感器,其中每个核心靠近至少一个温度传感器。 该处理器还包括一个功率控制单元(PCU),其包括用于接收包括来自每个温度传感器的相应温度值的温度数据的温度逻辑。 响应于温度数据的最高温度值超过阈值的指示,温度逻辑是根据基于多个核心中的至少两个的指令执行特性的确定的策略来调整多个域频率。 每个域频率与包括多个核心中的至少一个核心的对应域相关联,并且每个域频率是可独立调整的。 描述和要求保护其他实施例。
    • 7. 发明申请
    • FLUSHING AND RESTORING CORE MEMORY CONTENT TO EXTERNAL MEMORY
    • 将外部存储器的内核存储器的内存清理和恢复
    • WO2016209476A1
    • 2016-12-29
    • PCT/US2016/033961
    • 2016-05-24
    • INTEL CORPORATION
    • GENDLER, AlexanderBERKOVITS, ArielMISHAELI, MichaelSHULMAN, NadavDESAI, SameerREHANA, ShaniANATI, IttaiSHAFI, Hisham
    • G06F15/78G06F1/32G06F12/06G06F11/20
    • G06F1/3287G06F12/0804G06F12/0868G06F12/0888G06F12/1433G06F2212/1052G06F2212/311G06F2212/621
    • A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.
    • 描述了分别将外部存储器和/或从外部存储器内核心存储器内容清理和恢复的方法和装置。 在一个实施例中,该装置是包括多个处理器核心的集成电路,所述多个处理核心包括一个核心,其具有可操作以存储一个核心数据的第一存储器,所述一个核心将数据从第一存储器存储到 响应于接收到一个核心将从第一低功率空闲状态转换到第二低功率空闲状态的第一指示,并且接收到从一个核心外部产生的第二指示,该第二存储器位于处理器的外部,指示该 一个核心是将来自第一存储器的数据存储到第二存储器,存储数据的第二存储器中的位置可由一个核心访问,并且IC中的其他处理器核心不可访问; 以及耦合到所述多个核心并位于所述多个核心外部的电力管理控制器。