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1. 发明申请

WO2018063752A1 MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL 审中-公开
标题翻译：用于计算机处理器控制的多级磁盘
公开(公告)号：WO2018063752A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050044
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： RAJWAN, Doron , ROTEM, Efraim , WEISSMANN, Eliezer , ANANTHAKRISHNAN, Avinash N. , SHAPIRA, Dorit
IPC分类号： G06F13/16
CPC分类号： G06F1/3228 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3293 , G06F17/5054 , G06F2217/78 , G06F2217/80
摘要： In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括处理核心和中央控制单元，以便：同时执行外部控制回路和内部控制回路，其中外部控制回路将整体监视处理器并且其中所述内部控制回路将监视包括在所述处理器中的第一处理核心; 基于外部控制回路确定包括在处理器中的第一处理核的第一控制动作; 基于所述内部控制回路确定所述处理器中包括的所述第一处理核心的第二控制动作; 基于所述第一控制动作和所述第二控制动作的比较，选择所述第一控制动作和所述第二控制动作中的一个作为选择的控制动作; 并将选择的控制动作应用于第一处理核心。描述并要求保护其他实施例。

2. 发明申请

WO2022067120A1 HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2022067120A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/052085
申请日：2021-09-24
申请人： INTEL CORPORATION
发明人： GARG, Vivek , VARMA, Ankush , SISTLA, Krishnakanth , GUPTA, Nikhil , BALIGAR, Nikethan Shivanand , WANG, Stephen , PALIT, Nilanjan , KAM, Timothy , PURANDARE, Adwait , GUPTA, Ujjwal , CHEN, Stanley , SHAPIRA, Dorit , VENUGOPAL, Shruthi , CHEMUDUPATI, Suresh , PARIKH, Rupal , DEHAEMER, Eric , SAMPATH, Pavithra , KANDULA, Phani Kumar , BANSAL, Yogesh , MULLA, Dean , TULANOWSKI, Michael , HAAKE, Stephen , HERDRICH, Andrew , DAS, Ripan
IPC分类号： G06F1/3203 , G06F1/30 , G06F1/26 , G06F9/50
摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

3. 发明申请

WO2018236543A1 DYNAMIC MAXIMUM FREQUENCY LIMIT FOR PROCESSING CORE GROUPS 审中-公开
公开(公告)号：WO2018236543A1
公开(公告)日：2018-12-27
申请号：PCT/US2018/034568
申请日：2018-05-25
申请人： INTEL CORPORATION
发明人： AL-RAWI, Asma H. , ARDANAZ, Federico , EASTEP, Jonathan M. , SHAPIRA, Dorit , SISTLA, Krishnakanth V. , GUPTA, Nikhil , SRINIVASAN, Vasudevan , MACNAMARA, Chris
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/06 , G06F1/04 , G06F1/08 , G06F1/324 , G06F9/4812 , G06F9/5044 , G06F9/505 , G06F9/5094 , G06F2209/5022 , G06F2209/504
摘要： An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

4. 发明申请

WO2016025095A1 BALANCED CONTROL OF PROCESSOR TEMPERATURE 审中-公开
标题翻译：加工温度平衡控制
公开(公告)号：WO2016025095A1
公开(公告)日：2016-02-18
申请号：PCT/US2015/038125
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： ROSENZWEIG, Nir , RAJWAN,, Doron , SHAPIRA, Dorit , SHULMAN, Nadav , ZIV, Tomer
IPC分类号： G06F1/26 , G06F1/32 , G06F1/20
CPC分类号： G06F1/206 , G01K1/026 , G01K13/00 , G06F1/3206 , G06F1/3234 , G06F1/324
摘要： In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心和多个温度传感器，其中每个核心靠近至少一个温度传感器。该处理器还包括一个功率控制单元（PCU），其包括用于接收包括来自每个温度传感器的相应温度值的温度数据的温度逻辑。响应于温度数据的最高温度值超过阈值的指示，温度逻辑是根据基于多个核心中的至少两个的指令执行特性的确定的策略来调整多个域频率。每个域频率与包括多个核心中的至少一个核心的对应域相关联，并且每个域频率是可独立调整的。描述和要求保护其他实施例。

5. 发明申请

WO2013032705A2 DETERMINING AN EFFECTIVE STRESS LEVEL ON A PROCESSOR 审中-公开
标题翻译：确定处理器上的有效应力水平
公开(公告)号：WO2013032705A2
公开(公告)日：2013-03-07
申请号：PCT/US2012/050895
申请日：2012-08-15
申请人： INTEL CORPORATION , SHAPIRA, Dorit , ROTEM, Efraim , MORAN, Douglas, R.
发明人： SHAPIRA, Dorit , ROTEM, Efraim , MORAN, Douglas, R.
IPC分类号： G06F1/00 , G06F1/26 , G06F13/00
CPC分类号： G06F11/3058 , G06F11/3024
摘要： In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心和耦合到核心的功率控制单元（PCU）。 PCU具有应力检测器以接收处理器正在工作的电压和温度，并且可以计算有效的可靠性应力，在诸如个人计算机，服务器计算机，平板电脑的计算系统的多个引导周期内维持有效可靠性应力，智能手机或任何其他计算平台，并且基于有效可靠性应力来控制处理器的一个或多个操作参数。描述并要求保护其他实施例。

6. 发明申请

WO2018063750A1 GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA 审中-公开
标题翻译：用平均数据产生处理器中断
公开(公告)号：WO2018063750A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050036
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , SHRALL, Jeremy J. , GANAPATHY, Deepak , SHAPIRA, Dorit
IPC分类号： G06F9/48
摘要： In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的至少一个执行单元以及中断产生单元。中断产生单元可以用于：在第一时间窗口上的多个时间点接收指示用于存储器单元的热状态值的多个值; 基于指示存储器单元中的热状态值的多个值来确定运行平均值; 并且响应于确定运行平均值已经超过高热状态阈值，生成指示处理器中的高热状态事件的热中断。描述并要求保护其他实施例。

7. 发明申请

WO2017105593A1 METHOD AND APPARATUS FOR PROVIDING POWER STATE INFORMATION USING IN-BAND SIGNALING 审中-公开
标题翻译：使用带内信令提供电力状态信息的方法和设备
公开(公告)号：WO2017105593A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/055565
申请日：2016-10-05
申请人： INTEL CORPORATION
发明人： RAJWAN, Doron , SHAPIRA, Dorit , FEIT, Itai , SHULMAN, Nadav , ROTEM, Efraim (Efi) , KUZI, Tal , WEISSMANN, Eliezer , ZIV, Tomer , ROSENZWEIG, Nir
IPC分类号： G06F1/32 , G06F11/30
CPC分类号： G06F1/3253 , G06F1/3287 , G06F1/3296 , G06F13/4282
摘要： A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.
摘要翻译：描述了一种使用带内信令提供功率状态信息的方法和设备。在一个实施例中，集成电路（IC）设备包括控制器，其可操作以接收来自平台控制总线的命令，所述命令请求与关于所述IC所驻留的功率状态的信息无关的数据; 以及控制逻辑，其可操作以获得数据以包括在对所述命令的响应中，其中所述控制器可操作以通过总线发送所述响应，所述响应包含响应于所述命令的所述数据的至少一部分并且包含所述数据的功率状态信息 IC。

8. 发明申请

WO2017083020A1 DYNAMICALLY OPTIMIZING POWER MANAGEMENT OPERATIONAL PARAMETERS OF A PROCESSOR 审中-公开
标题翻译：动态优化处理器的电力管理运行参数
公开(公告)号：WO2017083020A1
公开(公告)日：2017-05-18
申请号：PCT/US2016/053623
申请日：2016-09-25
申请人： INTEL CORPORATION
发明人： ZOBEL, Shmuel , LEVIT, Maxim , ROTEM, Efraim , WEISSMANN, Eliezer , RAJWAN, Doron , SHAPIRA, Dorit , SHULMAN, Nadav
IPC分类号： G06F1/32 , G06K7/02
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种处理器包括至少一个核心，至少一个热传感器以及功率控制器，所述功率控制器包括第一逻辑，以动态地更新所述至少一个核心启用的持续时间处于涡轮模式。描述并要求保护其他实施例。

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