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1. 发明申请

WO2018004950A1 ENERGY-EFFICIENT BITCOIN MINING HARDWARE ACCELERATORS 审中-公开
标题翻译：能源效率比特币矿山硬件加速器
公开(公告)号：WO2018004950A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035195
申请日：2017-05-31
申请人： INTEL CORPORATION
发明人： SURESH, Vikram B. , SATPATHY, Sudhir K. , MATHEW, Sanu K.
IPC分类号： H04L9/06 , G06Q20/12
CPC分类号： H04L9/0643 , H04L9/0618 , H04L2209/20 , H04L2209/30 , H04L2209/38 , H04L2209/56
摘要： A processing system includes a processor to construct an input message comprising a target value and a nonce and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash, the hardware accelerator is to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, calculate a plurality of speculative computation bits using a plurality of bits of the state data, and transmit the plurality of speculative computation bits to the processor.
摘要翻译：处理系统包括：处理器，用于构造包括目标值和随机数的输入消息;以及硬件加速器，其通信地耦合到处理器，实现多个电路以执行阶段1安全散列算法（SHA）散列和阶段2 SHA散列，其中为了执行阶段2 SHA散列，硬件加速器将对存储在与阶段2 SHA SHA相关联的多个寄存器中的状态数据执行多轮压缩电路，使用输入值来计算多个推测计算比特，使用状态数据的多个比特计算多个推测计算比特，并将多个推测计算比特发送到处理器。

2. 发明申请

WO2017105710A1 COMPRESSED DATA DECODER 审中-公开
标题翻译：压缩数据解码器
公开(公告)号：WO2017105710A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061951
申请日：2016-11-15
申请人： INTEL CORPORATION
发明人： SATPATHY, Sudhir K. , MATHEW, Sanu K. , SURESH, Vikram B.
IPC分类号： G06F9/30
CPC分类号： H03M7/4037 , H03M7/6005
摘要： A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value generator, and a decoder. The code information array includes a pre-computed code length counter and a pre-computed last code. The matching logic unit includes logic using the code information array to match a segment of a payload of the compressed data with a matching code length and a matching code index. The code value generator includes logic to translate the matching code index into a code value. The decoder includes logic to generate decompressed data from the code value and the matching code length.
摘要翻译：处理器包括用于解码压缩数据的执行单元。执行单元包括代码信息数组，匹配逻辑单元，代码值生成器和解码器。代码信息数组包括预先计算的代码长度计数器和预先计算的最后代码。匹配逻辑单元包括使用代码信息阵列的逻辑，以将压缩数据的有效载荷的分段与匹配代码长度和匹配代码索引进行匹配。代码值生成器包括将匹配代码索引转换为代码值的逻辑。解码器包括从码值和匹配码长度生成解压缩数据的逻辑。

3. 发明申请

WO2014209391A1 A METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) 审中-公开
标题翻译：用于芯片上同步电路切换网络的方法，装置和系统（NOC）
公开(公告)号：WO2014209391A1
公开(公告)日：2014-12-31
申请号：PCT/US2013/048748
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： CHEN, Gregory K. , ANDERS, Mark A. , KAUL, Himanshu , SATPATHY, Sudhir K. , KRISHNAMURTHY, Ram K.
IPC分类号： H04L12/50
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/7825 , H04L12/46 , H04L49/109 , H04L67/10 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。描述和要求保护其他实施例。

4. 发明申请

WO2018063626A1 LINEAR MASKING CIRCUITS FOR SIDE-CHANNEL IMMUNIZATION OF ADVANCED ENCRYPTION STANDARD HARDWARE 审中-公开
标题翻译：用于先进加密标准硬件的侧信道免疫的线性屏蔽电路
公开(公告)号：WO2018063626A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/048754
申请日：2017-08-25
申请人： INTEL CORPORATION
发明人： KUMAR, Raghavan , MATHEW, Sanu K. , VARNA, Avinash L. , SURESH, Vikram B. , SATPATHY, Sudhir K.
IPC分类号： H04L9/06 , H04L9/08 , G06F7/58
摘要： Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.
摘要翻译：描述了一种包括S盒电路的设备，所述S盒电路可操作以根据高级加密标准（AES）Rijndael S盒矩阵将输入上的值转换为输出上的值。该设备还包括伪随机数生成（PRG）电路，该伪随机数生成（PRG）电路可操作以在第一输出上提供伪随机数序列，并在第二输出上提供该序列的注册副本。该设备还包括掩模电路，其可操作以提供S盒电路的输出上的值与PRG电路的第一输出上的值的XOR。该设备另外包括掩模去除电路，该掩模去除电路可操作以提供数据寄存器电路的输出上的值，耦合到键寄存器电路的输出的值以及PRG电路的第二输出上的值的XOR。 / p>

5. 发明申请

WO2018063483A1 PHYSICALLY UNCLONABLE CIRCUIT HAVING A PROGRAMMABLE INPUT FOR IMPROVED DARK BIT MASK ACCURACY 审中-公开
标题翻译：具有可编程输入的物理上不可回路的电路用于改进的黑色位掩模精度
公开(公告)号：WO2018063483A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/043949
申请日：2017-07-26
申请人： INTEL CORPORATION
发明人： MATHEW, Sanu K. , SATPATHY, Sudhir K. , SURESH, Vikram B.
IPC分类号： H03K19/177 , G06F21/44
CPC分类号： H03K19/17764 , H03K19/003 , H03K19/1776
摘要： An apparatus is described. The apparatus includes a physically unclonable (PUF) circuit having a programmable input. The programmable input is to receive a value that caused the PUF circuit to strengthen its stability or strengthen its instability.
摘要翻译：描述了一种装置。该装置包括具有可编程输入的物理不可克隆（PUF）电路。可编程输入接收的值会导致PUF电路增强其稳定性或增强其不稳定性。

6. 发明申请

WO2018004943A1 OPTIMIZED SHA-256 DATAPATH FOR ENERGY-EFFICIENT HIGH-PERFORMANCE BITCOIN MINING 审中-公开
标题翻译：优化的SHA-256数据通道用于高效高性能比卡因矿业
公开(公告)号：WO2018004943A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035136
申请日：2017-05-31
申请人： INTEL CORPORATION
发明人： SURESH, Vikram B. , SATPATHY, Sudhir K. , MATHEW, Sanu K.
IPC分类号： G06F13/14
CPC分类号： H04L9/0643 , G09C1/00 , H04L2209/12
摘要： A processing system includes a processor to construct an input message comprising a plurality of padding bits and a hardware accelerator, communicatively coupled to the processor, comprising a first plurality of circuits to perform a stage-1 secure hash algorithm (SHA) hash based on the input message, wherein the hardware accelerator comprises a first data path coupled between a first reference node and a first input node of the first plurality of circuits to feed a first padding bit of the plurality of padding bits to the first input node.
摘要翻译：处理系统包括：处理器，用于构建包括多个填充位的输入消息和通信地耦合到处理器的硬件加速器，所述处理器包括第一多个电路以执行阶段1安全散列算法（SHA）散列，其中所述硬件加速器包括耦合在所述第一多个电路中的第一参考节点和第一输入节点之间的第一数据路径，以将所述多个填充比特中的第一填充比特馈送到第一个输入节点。

7. 发明申请

WO2018063623A1 A NON-LINEAR PHYSICALLY UNCLONABLE FUNCTION (PUF) CIRCUIT WITH MACHINE-LEARNING ATTACK RESISTANCE 审中-公开
标题翻译：具有机器学习攻击抵抗能力的非线性物理无功功能（PUF）电路
公开(公告)号：WO2018063623A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/048697
申请日：2017-08-25
申请人： INTEL CORPORATION
发明人： SURESH, Vikram B. , MATHEW, Sanu K. , SATPATHY, Sudhir K.
IPC分类号： H03K19/0948 , H04L9/32
CPC分类号： H04L9/002 , H03K19/003 , H04L9/3278
摘要： Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective response bits of an authentication code in response to a challenge bit string. The PUF cells may include a pair of cross-coupled inverters, the individual inverters including independently selectable pull-down or pull-up legs. One of the pull-up or pull-down legs of each inverter may be selectively activated based on the challenge bit string. The PUF cells may further include first and second configurable clock delay circuits to pass respective clock signals to pre-charge transistors of the PUF cell. A dark bit masking circuit may generate a soft dark bit mask for the PUF circuit. Other embodiments may be described and claimed.
摘要翻译：实施例包括用于物理不可克隆功能（PUF）电路的装置，方法和系统。 PUF电路可以包括PUF单元的阵列以响应于挑战比特串来生成认证码的相应响应比特。 PUF单元可以包括一对交叉耦合的反相器，各个反相器包括独立可选择的下拉或上拉腿。基于询问位串，可以选择性地激活每个反相器的上拉或下拉腿之一。 PUF单元还可以包括第一可配置时钟延迟电路和第二可配置时钟延迟电路，以将各个时钟信号传递给PUF单元的预充电晶体管。暗位掩码电路可以为PUF电路生成软暗位掩码。其他实施例可以被描述和要求保护。

8. 发明申请

WO2018004949A1 A LOW CLOCK-ENERGY 3-PHASE LATCH-BASED CLOCKING SCHEME 审中-公开
标题翻译：一种低时钟能量三相锁定式锁定方案
公开(公告)号：WO2018004949A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035191
申请日：2017-05-31
申请人： INTEL CORPORATION
发明人： SURESH, Vikram B. , SATPATHY, Sudhir K. , MATHEW, Sanu K.
IPC分类号： G06F9/30
CPC分类号： G06F1/06 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/125 , H04L2209/38
摘要： A processing system includes a processor and a hardware accelerator, communicatively coupled to the processor, comprising a plurality of circuits to perform a plurality rounds of computation, wherein the plurality of circuits comprise a first set of level- sensitive latches enabled by a first clock signal to store data associated with a first round of the plurality of rounds of computation and a second set of level-sensitive latches enabled by a second clock signal to store data associated with a second round of the plurality of rounds of computation, and wherein a duty cycle of the first clock signal and a duty cycle of the second clock signal are non-overlapping.
摘要翻译：处理系统包括通信地耦合到处理器的处理器和硬件加速器，该处理器包括多个电路以执行多轮计算，其中多个电路包括第一组电平转换器，所述敏感锁存器由第一时钟信号启用以存储与所述多轮计算的第一轮相关联的数据以及由第二时钟信号启用的第二组电平锁存器以存储与所述多个循环中的第二轮相关联的数据并且其中第一时钟信号的占空比和第二时钟信号的占空比是非重叠的。

9. 发明申请

WO2017112351A1 HARDWARE APPARATUSES AND METHODS FOR DATA DECOMPRESSION 审中-公开
标题翻译：硬件设备和数据减压方法
公开(公告)号：WO2017112351A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063801
申请日：2016-11-27
申请人： INTEL CORPORATION
发明人： SATPATHY, Sudhir K. , GUILFORD, James D. , MATHEW, Sanu K. , GOPAL, Vinodh , SURESH, Vikram B.
IPC分类号： G06F9/30
CPC分类号： H03M7/3082 , G06F9/3877 , G06F9/46 , H03M7/4037 , H03M7/6005 , H03M7/6011 , H03M7/6017 , H03M7/6052
摘要： Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.
摘要翻译：描述涉及数据解压缩的方法和设备。在一个实施例中，硬件处理器包括用于执行线程和卸载用于包括文字代码，长度代码和距离代码的编码压缩数据流的解压缩线程的核心以及用于执行解压缩线程的硬件解压缩加速器以选择性地将编码的压缩数据流提供给第一电路以将文字码串行地解码为文字符号，将长度码串行解码为长度符号，并且将距离码串行解码成距离符号，并且选择性地提供编码的，将压缩数据流传送到第二电路，以从表格中查找文字代码的文字符号，从表格中查找长度代码的长度符号，并从表格中查找距离代码的距离符号。 / p>

10. 发明申请

WO2017058374A2 SMS4 ACCELERATION PROCESSORS HAVING ROUND CONSTANT GENERATION 审中-公开
标题翻译： SMS4加速加速器具有恒定的恒定发电
公开(公告)号：WO2017058374A2
公开(公告)日：2017-04-06
申请号：PCT/US2016/047054
申请日：2016-08-15
申请人： INTEL CORPORATION
发明人： SATPATHY, Sudhir K. , MATHEW, Sanu K. , YAP, Kirk S. , GOPAL, Vinodh
CPC分类号： H04L9/0675 , G09C1/00 , H04L9/0631 , H04L9/14 , H04L2209/24 , H04L2209/34
摘要： A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic generates a plurality of variable bits of the output bit sequence. The processing logic produces the output bit sequence including the identified constant bits and the generated plurality of variable bits.
摘要翻译：处理系统包括可操作地耦合到存储器的存储器和处理逻辑。处理逻辑识别输出比特序列的一个或多个恒定比特。处理逻辑产生输出位序列的多个可变位。处理逻辑产生包括所识别的常数比特和所生成的多个可变比特的输出比特序列。

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