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1. 发明申请

WO2017052572A1 GRAPHENE BARRIER FOR ELECTRICAL INTERCONNECTS 审中-公开
标题翻译：用于电气互连的石墨屏障
公开(公告)号：WO2017052572A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052147
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： CAUDILLO, Roman , MAESTRE CARO, Aranzazu
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H01L21/76864 , H01L21/76843 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/53276
摘要： Techniques are disclosed for producing graphitic barrier layers that encapsulate or otherwise isolate a metal interconnect feature from adjacent insulator or dielectric materials. The techniques can include an on-chip synthesis method in which barrier layer precursor materials, for example, hydrocarbon-based self-assembled monolayers, are positioned between a dielectric feature and an electrically conductive metal line. Through a treatment process, such as thermal annealing, the barrier layer precursor materials are converted into a graphitic barrier layer that comprises graphene and, in some cases, is a graphene monolayer. The disclosed graphitic barrier layers may be atomically thin, have a substantially uniform thickness and may optionally conduct charge, thereby allowing the barrier layer to serve as a current shunt, capable of supporting high current densities.
摘要翻译：公开了用于生产石墨阻挡层的技术，其封装或以其他方式将金属互连特征与相邻绝缘体或电介质材料隔离。这些技术可以包括片上合成方法，其中阻挡层前体材料例如基于烃的自组装单层定位在电介质特征和导电金属线之间。通过诸如热退火的处理工艺，将阻挡层前体材料转化成包括石墨烯的石墨阻挡层，并且在某些情况下是石墨烯单层。所公开的石墨阻挡层可以是原子上薄的，具有基本均匀的厚度，并且可以任选地导电，从而允许阻挡层用作能够支持高电流密度的电流分流。

2. 发明申请

WO2018063281A1 GRAPHENE NANORIBBON INTERCONNECTS AND INTERCONNECT LINERS 审中-公开
公开(公告)号：WO2018063281A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054650
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin , CAUDILLO, Roman , CHAWLA, Jasmeet, S. , TORRES, Jessica, M. , MAESTRE CARO, Aranzazu
IPC分类号： H01L21/768 , H01L29/16 , H01L21/02 , H01L29/06
摘要： Graphitic nanoribbon interconnects are described. The graphitic nanoribbon interconnects are fabricated by forming a graphitic layer (such as graphene) on a metal feature growth catalyst. The metal feature growth catalyst is selectively removed, leaving a graphitic nanoribbon remaining as the interconnect. Graphitic nanoribbon interconnects have a thickness of from 0.3 nanometers (nm) to 2 nm and a height of at least 40 nm. The conductive graphitic nanoribbon interconnect overcomes the need to include conventionally composed interconnect liners. Furthermore, the reduced feature size of the graphitic nanoribbon interconnect compared to conventional liners enables greater interconnect density and semiconductor device density.

3. 发明申请

WO2017095432A1 FORMING INTERCONNECTS WITH SELF-ASSEMBLED MONOLAYERS 审中-公开
标题翻译：形成与自组装单层膜的相互连接
公开(公告)号：WO2017095432A1
公开(公告)日：2017-06-08
申请号：PCT/US2015/063875
申请日：2015-12-04
申请人： INTEL CORPORATION , MAESTRE CARO, Aranzazu , CHEBIAM, Ramanan V.
发明人： MAESTRE CARO, Aranzazu , CHEBIAM, Ramanan V.
IPC分类号： H01L21/4763 , H01L21/31
CPC分类号： H01L21/3105
摘要： Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner can be formed on a dielectric substrate. A protective layer can be formed on the SAM liner. The protective layer can double as a seed layer for electroless deposition of an interconnect metal. The interconnect metal can be deposited on the protective layer using electroless deposition. The dielectric, with the SAM liner, the protective layer, and the interconnect metal can be annealed to reflow the interconnect metal into trenches formed in the dielectric.
摘要翻译：本公开的实施例涉及使用SAM衬垫来促进用于集成电路互连的金属的无电沉积。 SAM衬垫可以形成在电介质衬底上。可以在SAM衬垫上形成保护层。保护层可以兼作用于无电沉积互连金属的晶种层。互连金属可以使用无电沉积沉积在保护层上。具有SAM内衬，保护层和互连金属的电介质可以退火以将互连金属回流到电介质中形成的沟槽中。

4. 发明申请

WO2018118082A1 GRAPHITIC LINERS FOR INTEGRATED CIRCUIT DEVICES 审中-公开
公开(公告)号：WO2018118082A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068512
申请日：2016-12-23
申请人： INTEL CORPORATION
发明人： SINGH, Kanwaljit , CHAWLA, Jasmeet S. , TORRES, Jessica M. , CAUDILLO, Roman , LIN, Kevin L. , MAESTRE CARO, Aranzazu
IPC分类号： H01L21/768 , H01L29/16 , H01L21/02
CPC分类号： H01L23/53266 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L23/5226 , H01L23/53209 , H01L23/53238
摘要： Disclosed herein are graphitic liners for integrated circuit (IC) devices, as well as related devices and methods. For example, disclosed herein are liners that include graphene having a quality gradient, multi-layer liners (e.g., including metal and graphene layers), and liners that line the sidewalls of a via while leaving a bottom of the via open for direct contact with a lower conductive structure.

5. 发明申请

WO2018063289A1 GRAPHENE NANORIBBON INTERCONNECTS AND INTERCONNECT LINERS 审中-公开
标题翻译：石墨烯纳米带互连和互连衬底
公开(公告)号：WO2018063289A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054675
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin , CAUDILLO, Roman , CHAWLA, Jasmeet S. , TORRES, Jessica M. , MAESTRE CARO, Aranzazu
IPC分类号： H01L21/768 , H01L21/02 , H01L29/06 , H01L29/16
摘要： Graphitic nanoribbon interconnects are described. The graphitic nanoribbon interconnects are fabricated by forming a graphitic layer (such as graphene) on a metal feature growth catalyst. The metal feature growth catalyst is selectively removed, leaving a graphitic nanoribbon remaining as the interconnect. Graphitic nanoribbon interconnects have a thickness of from 0.3 nanometers (nm) to 2 nm and a height of at least 40 nm. The conductive graphitic nanoribbon interconnect overcomes the need to include conventionally composed interconnect liners. Furthermore, the reduced feature size of the graphitic nanoribbon interconnect compared to conventional liners enables greater interconnect density and semiconductor device density.
摘要翻译：描述了石墨纳米带互连。石墨纳米带互连通过在金属特征生长催化剂上形成石墨层（例如石墨烯）来制造。选择性去除金属特征生长催化剂，留下石墨纳米带作为互连。石墨纳米带互连具有0.3纳米（nm）至2nm的厚度和至少40nm的高度。导电石墨纳米带互连克服了包括常规组成的互连衬里的需要。此外，与常规衬垫相比，石墨纳米带互连的减小的特征尺寸能够实现更大的互连密度和半导体器件密度。

6. 发明申请

WO2017095485A1 SAM ASSISTED SELECTIVE E-LESS PLATING ON PACKAGING MATERIALS 审中-公开
标题翻译： SAM帮助包装材料选择性无电镀
公开(公告)号：WO2017095485A1
公开(公告)日：2017-06-08
申请号：PCT/US2016/046047
申请日：2016-08-08
申请人： INTEL CORPORATION
发明人： HUA, Fay , MAESTRE CARO, Aranzazu
IPC分类号： B32B37/26 , B32B7/10 , B32B27/08 , B32B27/18
CPC分类号： H01L21/4846 , H01L23/49894
摘要： A method including activating an area of a polymer layer on a substrate with electromagnetic radiation; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with the self-assembled monolayer; and reacting the self-assembled monolayer with a conductive material. A method including activating an area of a polymer dielectric layer on a substrate with electromagnetic radiation, the area selected for an electrically conductive line; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with a catalyst; and electroless plating a conductive material on the self-assembled monolayer.
摘要翻译：包括利用电磁辐射激活衬底上的聚合物层的区域的方法; 修改激活区域; 在改性活性区域上形成自组装单层; 使自组装单层与自组装单层反应; 并使自组装单层与导电材料反应。一种方法，包括利用电磁辐射激活衬底上的聚合物电介质层的区域，所述区域选择用于导电线; 修改激活区域; 在改性活性区域上形成自组装单层; 使自组装单层与催化剂反应; 并在自组装单层上无电镀导电材料。

7. 发明申请

WO2018182637A1 BOTTOM-UP FILL USING BLOCKING LAYERS AND ADHESION PROMOTERS 审中-公开
公开(公告)号：WO2018182637A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025127
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： HOURANI, Rami , CLENDENNING, Scott B. , KLOSTER, Grant M. , MAESTRE CARO, Aranzazu , GSTREIN, Florian , CHOWDHURY, Akm Shaestagir , MAHDI, Tayseer
IPC分类号： H01L21/768
摘要： A device including a substrate formed of a material. The device includes a plurality of recessed features in a surface of the substrate, wherein the plurality of recessed features have an aspect ratio between 3:1-10:1, inclusive. The device includes a fill in the plurality of recessed features, wherein the fill is a second material that is different than the material of the substrate and wherein the fill covers sidewalls and bottom surfaces of the plurality of recessed features.

8. 发明申请

WO2018118081A1 GRAPHITIC LINERS FOR INTEGRATED CIRCUIT DEVICES 审中-公开
公开(公告)号：WO2018118081A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068511
申请日：2016-12-23
申请人： INTEL CORPORATION
发明人： CHAWLA, Jasmeet, S. , TORRES, Jessica, M. , CAUDILLO, Roman , LIN, Kevin, L. , MAESTRE CARO, Aranzazu , SINGH, Kanwaljit
IPC分类号： H01L21/768 , H01L29/16 , H01L21/02
CPC分类号： H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L23/5226 , H01L23/53209 , H01L23/53238 , H01L23/53266
摘要： Disclosed herein are graphitic liners for integrated circuit (IC) devices, as well as related devices and methods. For example, disclosed herein are liners that include graphene having a quality gradient, multi-layer liners (e.g., including metal and graphene layers), and liners that line the sidewalls of a via while leaving a bottom of the via open for direct contact with a lower conductive structure.

9. 发明申请

WO2018063272A1 GRAPHENE NANORIBBON INTERCONNECTS AND INTERCONNECT LINERS 审中-公开
标题翻译：石墨烯纳米带互连和互连衬底
公开(公告)号：WO2018063272A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054627
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin , CAUDILLO, Roman , BOJARSKI, Stephanie A. , MAESTRE CARO, Aranzazu , TORRES, Jessica M. , CHAWLA, Jasmeet S.
IPC分类号： H01L21/768 , H01L29/16
CPC分类号： H01L23/53276 , H01L21/768 , H01L29/16
摘要： Graphitic barrier layers for metal interconnects are described. The graphitic barrier layers are substantially conformal to a metal feature portion of an interconnect and have thicknesses in a range from 0.3 nanometers (nm) to 2 nm. This thickness is much less than the thickness of conventional diffusion barriers (e.g., tantalum nitride) which are in a range of from 5 nm to 10 nm. The thinner graphitic barrier layer improves the conductivity of the metal interconnect because proportionately more conductive metal can be deposited in the interconnect compared to conventionally (e.g., tantalum-based) lined interconnects. Furthermore, unlike conventional barriers layers which are poor electrical conductors, graphitic is conductive. This also improves the electrical conductivity of the interconnect as a whole.
摘要翻译：描述了用于金属互连的石墨阻挡层。石墨阻挡层基本上与互连的金属特征部分共形并具有0.3纳米（nm）至2nm范围内的厚度。该厚度远小于常规扩散阻挡层（例如氮化钽）的厚度，其范围为5nm至10nm。较薄的石墨阻挡层改善了金属互连的导电性，因为与常规（例如，基于钽的）内衬互连相比，可以在互连中沉积更多的导电金属。而且，不同于导电性差的传统阻挡层，石墨是导电的。这也提高了整个互连的导电性。

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