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1. 发明申请

WO2019139573A1 TECHNIQUES TO REDUCE SUBSTRATE COUPLING FOR MONOLITHICALLY INTEGRATED RF CIRCUITS 审中-公开
公开(公告)号：WO2019139573A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/013151
申请日：2018-01-10
申请人： INTEL CORPORATION
发明人： FISCHER, Paul, B. , THEN, Han, Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , LIN, Kevin
IPC分类号： H01L29/423 , H01L29/78 , H01L21/762 , H01L29/66
摘要： Techniques are disclosed for fabricating airgaps to explicitly suppress parasitic electrical pathways between devices through the use of selectively etchable materials or layers. Using such features, relatively high device densities can be achieved while still suppressing crosstalk between devices. In particular, selective etchable layers are incorporated into a fabrication process. Lithographically defined access holes or trenches are introduced to facilitate the selection of etchable regions.

2. 发明申请

WO2019066789A1 EPITAXIAL III-N NANORIBBON STRUCTURES FOR DEVICE FABRICATION 审中-公开
公开(公告)号：WO2019066789A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053584
申请日：2017-09-27
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , THEN, Han Wui , FISCHER, Paul , LIN, Kevin
IPC分类号： H01L29/778 , H01L29/06 , H01L29/45
摘要： A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.

3. 发明申请

WO2018063337A1 VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS 审中-公开
标题翻译： VIAS和GAPS在半导体互连中的应用
公开(公告)号：WO2018063337A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054818
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： LIN, Kevin , CHANDHOK, Manish
IPC分类号： H01L21/768
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/7682 , H01L21/76834 , H01L21/76897 , H01L23/5222 , H01L2221/1026
摘要： Systems and methods for maskless gap (for example, air gap) integration into multilayer interconnects having one or more interconnect lines (for example, metal interconnect lines) embedded in a dielectric layer of the interconnects are described. In various embodiments, the described systems and methods may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines (for example, metal interconnect lines) from electrical shorting during subsequent metal layer depositions, for example, during a fabrication sequence of the interconnects. Further, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps. Further, such gaps may be inherently self-aligned to the vias and/or spacer layers. Moreover, the gaps may act to reduce capacitance and thereby increase the performance (circuit timing, power consumption, etc.) of the interconnect.
摘要翻译：描述了用于将无掩模间隙（例如，气隙）集成到具有嵌入在互连的电介质层中的一个或多个互连线（例如，金属互连线）的多层互连中的系统和方法。在各种实施例中，所描述的系统和方法可用于减少互连中相邻通孔之间的电短路。在一个实施例中，可提供间隔物层以掩蔽互连中的层间电介质（ILD）的部分。例如，在互连的制造顺序期间，ILD的这些掩模部分可以保护相邻互连线之间的区域（例如，金属互连线）免于在后续金属层沉积期间的电短路。此外，通孔可以封闭间隙（例如，气隙）而不需要额外的掩蔽步骤。此外，这些间隙可以固有地与通孔和/或间隔层自对准。而且，这些间隙可以起到减小电容的作用，从而增加互连的性能（电路时序，功耗等）。

4. 发明申请

WO2017204821A1 SUBTRACTIVE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTS 审中-公开
标题翻译：减号插头和电脑插头用于线后端（BEOL）基于间隔器的互连
公开(公告)号：WO2017204821A1
公开(公告)日：2017-11-30
申请号：PCT/US2016/034624
申请日：2016-05-27
申请人： INTEL CORPORATION
发明人： LIN, Kevin , BRISTOL, Robert L. , SCHENKER, Richard E.
IPC分类号： H01L21/768
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76885 , H01L23/5226 , H01L23/528
摘要： Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
摘要翻译：描述了用于后端行线（BEOL）间隔件互连的带有光桶的减薄插塞和标签图案化。在一个实例中，用于半导体结构的线后端（BEOL）金属化层包括设置在衬底上方的层间电介质（ILD）层。多个导线沿着第一方向设置在ILD层中。导电接片布置在ILD层中，导电接片沿着与第一方向正交的第二方向耦合多条导线中的两条导线。导电通孔耦合到多个导电线中的一个，导电通孔上具有通孔硬掩模。 ILD层，多个导电线，导电接线片和通孔硬掩模中的每一个的最上表面彼此是平面的。

5. 发明申请

WO2016209293A1 TEXTILE PATTERNING FOR SUBTRACTIVELY-PATTERNED SELF-ALIGNED INTERCONNECTS, PLUGS, AND VIAS 审中-公开
标题翻译：分布式自对准互连，插头和VIAS的纺织图案
公开(公告)号：WO2016209293A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/038145
申请日：2015-06-26
申请人： INTEL CORPORATION , LIN, Kevin , BRISTOL, Robert Lindsey , MYERS, Alan M.
发明人： LIN, Kevin , BRISTOL, Robert Lindsey , MYERS, Alan M.
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , H01L21/0334 , H01L21/76801 , H01L21/76816 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L21/76897 , H01L23/5226
摘要： Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmaskS. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.
摘要翻译：本发明的实施例包括形成织物图案化硬掩模的方法。在一个实施例中，第一硬掩模和第二硬掩模以交替图案形成在互连层的顶表面上。然后可以在第一和第二硬掩模S上形成牺牲交叉光栅。在一个实施例中，去除未被牺牲交叉光栅覆盖的第一硬掩模的部分以形成第一开口，并且将第三硬掩模设置在第一开口中。实施例可以包括蚀刻通过未被牺牲交叉光栅覆盖的第二硬掩模的部分以形成第二开口。第二开口可以填充第四硬掩模。根据实施例，第一，第二，第三和第四硬掩模是相互蚀刻选择性的。在一个实施例中，可以去除牺牲交叉光栅。

6. 发明申请

WO2016209246A1 DORIC PILLAR SUPPORTED MASKLESS AIRGAP STRUCTURE FOR CAPACITANCE BENEFIT WITH UNLANDED VIA SOLUTION 审中-公开
标题翻译：多立支撑支撑的空中飞机结构，通过解决方案可以获得优势
公开(公告)号：WO2016209246A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037835
申请日：2015-06-25
申请人： INTEL CORPORATION , SINGH, Kanwal Jit , LIN, Kevin , BRISTOL, Robert Lindsey
发明人： SINGH, Kanwal Jit , LIN, Kevin , BRISTOL, Robert Lindsey
IPC分类号： H01L21/764 , H01L27/108
CPC分类号： H01L23/53295 , H01L21/764 , H01L21/76808 , H01L21/76816 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L23/49827 , H01L23/5222 , H01L23/5226
摘要： Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
摘要翻译：本发明的实施例包括具有浮动互连线的互连层和形成这种互连层的方法。在一个实施例中，在第一牺牲材料层中形成多个开口。可以在开口中形成导电孔和电介质柱。然后可以在柱，通孔和第一牺牲材料层之上形成第二牺牲材料层。在一个实施例中，在第二牺牲层的顶表面上形成可渗透的防蚀层。然后，实施例包括在第二牺牲材料层中形成互连线。在一个实施例中，在形成互连线之后，第一和第二牺牲材料层通过可渗透的阻挡层去除。根据一个实施例，然后可以用填充材料填充可渗透的防蚀层，以便硬化可渗透的防蚀层。

7. 发明申请

WO2016105422A1 STRUCTURE AND METHOD TO SELF ALIGN VIA TO TOP AND BOTTOM OF TIGHT PITCH METAL INTERCONNECT LAYERS 审中-公开
标题翻译：结构和方法通过顶部和底部的垂直金属互连层自对准
公开(公告)号：WO2016105422A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072392
申请日：2014-12-24
申请人： INTEL CORPORATION
发明人： SCHENKER, Richard E. , CHANDHOK, Manish , BRISTOL, Robert L. , KOBRINSKY, Mauro J. , LIN, Kevin
IPC分类号： H01L21/768 , H01L21/60
CPC分类号： H01L23/5226 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L21/7682 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/5283 , H01L23/53295
摘要： Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.
摘要翻译：本发明的实施例包括具有开口通孔的互连结构和与互连线自对准的通孔以及形成这种结构的方法。在一个实施例中，在层间电介质（ILD）中形成互连结构。可以在ILD中形成一个或多个第一互连线。互连结构还可以包括以与第一互连线交替模式布置的ILD中的一个或多个第二互连线。第一和第二互连线中的每一个的顶表面可以凹入ILD的顶表面下方。互连结构可以包括在一个或多个第一互连线上或在一个或多个第二互连线上形成的自对准开销通道。在一个实施例中，自对准开销通道的顶表面与ILD的顶表面基本共面。

8. 发明申请

WO2022093430A1 SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2022093430A1
公开(公告)日：2022-05-05
申请号：PCT/US2021/051146
申请日：2021-09-20
申请人： INTEL CORPORATION
发明人： LIN, Kevin , SATO, Noriyuki , TRONIC, Tristan A. , CHRISTENSON, Michael , JEZEWSKI, Christopher J. , CHEN, Jiun-Ruey , BLACKWELL, James , METZ, Matthew V. , RESHOTKO, Miriam , KABIR, Nafees , BIELEFELD, Jeffery , CHANDHOK, Manish , YOO, Hui Jae , KARPOV, Elijah V. , NAYLOR, Carl , CHEBIAM, Ramanan V.
IPC分类号： H01L27/06 , H01L27/02 , H01L21/8234 , H01L23/528 , H01L23/538
摘要： IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

9. 发明申请

WO2019132899A1 INTEGRATED CIRCUITS (ICS) WITH ELECTROMIGRATION (EM)-RESISTANT SEGMENTS IN AN INTERCONNECT LEVEL 审中-公开
公开(公告)号：WO2019132899A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068590
申请日：2017-12-27
申请人： INTEL CORPORATION
发明人： LIN, Kevin , JEZEWSKI, Christopher J. , CHANDHOK, Manish
IPC分类号： H01L21/768
摘要： Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.

10. 发明申请

WO2019132897A1 MULTIPLE LAYER METAL-INSULATOR-METAL (MIM) STRUCTURE 审中-公开
公开(公告)号：WO2019132897A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068587
申请日：2017-12-27
申请人： INTEL CORPORATION
发明人： LIN, Kevin
IPC分类号： H01L49/02 , H01L21/768
摘要： An apparatus is provided, which includes a stack of a first plurality of layers interleaved with a second plurality of layers. In an example, the first plurality of layers includes conductive material, and the second plurality of layers includes insulating material. In an example, the first plurality of layers includes an upper layer and lower layer. A first via may extend through at least a portion of the stack, where the first via may be in contact with the upper layer and the lower layer. A second via may extend through at least a portion of the stack, where the second via may be isolated from the upper layer and lower layer.

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