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1. 发明申请

WO2017099730A1 WIRELESS INTERCONNECTS ON FLEXIBLE CABLES BETWEEN COMPUTING PLATFORMS 审中-公开
标题翻译：计算平台间灵活电缆的无线互连
公开(公告)号：WO2017099730A1
公开(公告)日：2017-06-15
申请号：PCT/US2015/064511
申请日：2015-12-08
申请人： INTEL CORPORATION
发明人： KAMGAING, Telesphor , DISCHLER, Richard J.
IPC分类号： G06F1/16 , G06F15/17
CPC分类号： G06F1/16 , H05K1/0274 , H05K1/147 , H05K2201/045 , H05K2201/046
摘要： Wireless interconnects are shown on flexible cables for communication between computing platforms. One example has an integrated circuit chip, a package substrate to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components, a cable on the package substrate coupled to the integrated circuit chip at one end, a radio chip on the cable coupled to the cable at the other end, the radio chip to modulate data over a carrier and to transmit the modulated data, and a waveguide transition coupled to a dielectric waveguide to receive the transmitted modulated data from the radio and to couple it into the waveguide, the waveguide to carry the modulated data to an external component.
摘要翻译：无线互连显示在灵活的电缆上用于计算平台之间的通信。一个示例具有集成电路芯片，用于承载集成电路芯片的封装衬底，具有用于将集成电路芯片连接到外部组件的导电连接器的封装衬底，在一端处耦合到集成电路芯片的封装衬底上的电缆，电缆上的无线电芯片在另一端耦合到电缆，无线电芯片在载波上调制数据并传输调制的数据，以及耦合到介质波导的波导转换以接收来自无线电的传输的调制数据，以及将其耦合到波导中，波导将调制数据传送到外部组件。

2. 发明申请

WO2018063708A1 FABRICATION PROCESS FOR RIBBON BUNDLED MILLIMETER-WAVEGUIDE 审中-公开
标题翻译：带状束毫米波导的制造工艺
公开(公告)号：WO2018063708A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049350
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： OSTER, Sasha N. , ALEKSOV, Aleksandar , DOGIAMIS, Georgios C. , KAMGAING, Telesphor , ELSHERBINI, Adel A. , LIFF, Shawna M. , SWAN, Johanna M. , RAWLINGS, Brandon M. , DISCHLER, Richard J.
IPC分类号： G02B6/44 , G02B6/10
CPC分类号： H01P3/122 , H01P3/14 , H01P3/16 , H01P11/006
摘要： A method of making a waveguide ribbon that includes a plurality of waveguides comprises joining a first sheet of dielectric material to a first conductive sheet of conductive material, patterning the first sheet of dielectric material to form a plurality of dielectric waveguide cores on the first conductive sheet, and coating the dielectric waveguide cores with substantially the same conductive material as the conductive sheet to form the plurality of waveguides.
摘要翻译：制造包括多个波导的波导带的方法包括将第一片介电材料接合到第一导电材料的导电片，图案化第一片介电材料以形成多个在第一导电片上形成电介质波导芯，并且用与导电片基本上相同的导电材料涂覆电介质波导芯以形成多个波导。

3. 发明申请

WO2018063560A1 WAVEGUIDE BUNDLE FABRICATION IN SUSPENDED MEDIA 审中-公开
标题翻译：波导组件在悬挂式媒体中的制作
公开(公告)号：WO2018063560A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/047299
申请日：2017-08-17
申请人： INTEL CORPORATION
发明人： DOGIAMIS, Georgios C. , OSTER, Sasha N. , KAMGAING, Telesphor , ELSHERBINI, Adel A. , SWAN, Johanna M. , LIFF, Shawna M. , ALEKSOV, Aleksandar , RAWLINGS, Brandon M. , DISCHLER, Richard J.
IPC分类号： G02B6/10 , G06F13/18 , G02B6/12
CPC分类号： H01P3/122 , G06F1/182 , H01P3/14 , H01P3/16 , H01P11/006
摘要： An apparatus comprises a plurality of waveguides, wherein the waveguides include a dielectric material; an outer shell; and a supporting feature within the outer shell, wherein the waveguides are arranged separate from each other within the outer shell by the supporting feature.
摘要翻译：一种设备包括多个波导，其中波导包括电介质材料; 外壳; 以及在外壳内的支撑特征，其中波导通过支撑特征彼此分离地布置在外壳内。

4. 发明申请

WO2018009171A1 RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING 审中-公开
标题翻译： RLINK - 模切通道互连配置以改善信号传输
公开(公告)号：WO2018009171A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040912
申请日：2016-07-02
申请人： INTEL CORPORATION , AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
发明人： AYGUN, Kemal , DISCHLER, Richard J. , MORRISS, Jeff C. , QIAN, Zhiguo , GOMES, Wilfred , ZHANG, Yu Amos , VISWANATH, Ram S. , SWAMINATHAN, Rajasekaran Raja , SRINIVASAN, Sriram , MEKONNEN, Yidnekachew S. , GANESAN, Sanka Gans , ROYTMAN, Eduard , MANUSHAROW, Mathew J.
IPC分类号： H01L25/065 , H01L23/60 , H01L23/498 , H01L23/525 , H01L23/00
摘要： Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
摘要翻译：集成电路（IC）芯片裸片至裸片通道互连配置（用于其制造的系统及方法）可通过包括裸片上导入结构来改善进入并通过单端总线数据信号通信通道的信号传输; 片上互连功能; 封装内第一级裸片凸点设计和地面织带结构; 封装式高速水平数据信号传输线; 封装上垂直数据信号传输互连; 和/或封装内电光（EO）连接器，用于改进信号连接和通过延伸穿过一个或多个半导体器件封装器件的数据信号通道的传输，所述半导体器件封装器件可包括电光（EO））连接器，在该连接器上可以安装至少一个封装器件，和/或作为半导体器件封装在封装式封装配置中。

5. 发明申请

WO2017052628A1 COMPUTING APPARATUS WITH CLOSED COOLING LOOP 审中-公开
标题翻译：带封闭冷却环的计算机
公开(公告)号：WO2017052628A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052377
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： KULKARNI, Devdatta P. , DISCHLER, Richard J.
IPC分类号： H05K7/20 , G06F1/20
CPC分类号： G06F1/20 , G06F2200/201 , H05K7/20263 , H05K7/20772
摘要： The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a closed cooling loop thermally coupled to one or more processors disposed on a circuit board of the computing apparatus. The closed cooling loop circulates a dielectric fluid to absorb heat from the processor. A portion of the dielectric fluid is evaporated from the processor heat absorbed by the dielectric fluid. A heat exchanger is coupled to the circuit board and thermally coupled to the closed cooling loop. The heat exchanger is to include a coolant flow to remove heat from the dielectric fluid circulated through the portion of the closed cooling loop thermally coupled to the heat exchanger. A vapor portion of the dielectric fluid is condensed from the heat removed by the coolant flow. Other embodiments may be described and/or claimed.
摘要翻译：本公开描述了与具有热耦合到设置在计算设备的电路板上的一个或多个处理器的封闭冷却回路相关的计算设备的设备和方法的实施例。封闭的冷却回路循环介电流体以吸收来自处理器的热量。电介质流体的一部分从由介电流体吸收的处理器蒸发。热交换器耦合到电路板并热耦合到封闭的冷却回路。热交换器包括冷却剂流，以从热耦合到热交换器的封闭冷却回路部分循环的介电流体中除去热量。电介质流体的蒸气部分由冷却剂流除去的热量冷凝。可以描述和/或要求保护其他实施例。

6. 发明申请

WO2018136123A3 SWITCHABLE TOPOLOGY MACHINE 审中-公开
公开(公告)号：WO2018136123A3
公开(公告)日：2018-07-26
申请号：PCT/US2017/058011
申请日：2017-10-24
申请人： INTEL CORPORATION
发明人： BUTERA, William J. , STEELY, Simon C., Jr. , DISCHLER, Richard J.
IPC分类号： G06F15/173 , G06F9/38
摘要： Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.

7. 发明申请

WO2018136123A2 SWITCHABLE TOPOLOGY MACHINE 审中-公开
公开(公告)号：WO2018136123A2
公开(公告)日：2018-07-26
申请号：PCT/US2017/058011
申请日：2017-10-24
申请人： INTEL CORPORATION
发明人： BUTERA, William J. , STEELY, Simon C., Jr. , DISCHLER, Richard J.
IPC分类号： G06F15/173 , G06F9/38
CPC分类号： G06F15/17381 , G06F9/38 , G06F9/3897 , G06F15/17343
摘要： Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.

8. 发明申请

WO2018063388A1 METHODS FOR CONDUCTIVELY COATING MILLIMETER WAVEGUIDES 审中-公开
标题翻译：导电涂覆毫米波的方法
公开(公告)号：WO2018063388A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054977
申请日：2016-09-30
申请人： INTEL CORPORATION , ALEKSOV, Aleksandar , DOGIAMIS, Georgios C , KAMGAING, Telesphor Teles , OSTER, Sasha N. , ELSHERBINI, Adel A. , LIFF, Shawna M. , SWAN, Johanna M. , RAWLINGS, Brandon M. , DISCHLER, Richard J.
发明人： ALEKSOV, Aleksandar , DOGIAMIS, Georgios C , KAMGAING, Telesphor Teles , OSTER, Sasha N. , ELSHERBINI, Adel A. , LIFF, Shawna M. , SWAN, Johanna M. , RAWLINGS, Brandon M. , DISCHLER, Richard J.
IPC分类号： H01P3/16 , H01P3/12
CPC分类号： H01P3/16 , H01P3/122 , H01P11/002 , H01P11/006 , H01Q9/045 , H04L67/10
摘要： A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.
摘要翻译：一种形成波导的方法包括形成包括介电材料的细长波导芯; 以及在电介质芯的外表面周围布置导电片以在波导芯周围产生导电层。

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