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1. 发明申请

WO2017052758A1 HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO 审中-公开
标题翻译：用于优化压缩比的异构压缩架构
公开(公告)号：WO2017052758A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/044303
申请日：2016-07-27
申请人： INTEL CORPORATION
发明人： GUILFORD, James D. , GOPAL, Vinodh , WOLRICH, Gilbert M. , CUTTER, Daniel F.
IPC分类号： H03M7/30
CPC分类号： H03M7/40 , H03M7/30 , H03M7/3086
摘要： A processing device includes a storage device to store data and a processor to receive a token stream comprising a plurality of tokens generated based on a byte stream comprising a plurality of bytes, generate a graph comprising a plurality of nodes and edges based on the token stream, identify, based on the graph, a path between a first node associated with a beginning token of the token stream and an end node associated with a last token of the token stream, and perform variable-length encoding of a subset of tokens associated with the subset of nodes to generate an output data.
摘要翻译：处理装置包括存储数据的存储装置和处理器，用于接收包括基于包括多个字节的字节流生成的多个令牌的令牌流，基于令牌流生成包括多个节点和边的图形基于图形，识别与令牌流的开始令牌相关联的第一节点与与令牌流的最后一个令牌相关联的结束节点之间的路径，并且执行与该令牌流相关联的令牌子集的可变长度编码节点的子集来生成输出数据。

2. 发明申请

WO2017052864A1 LOOK-AHEAD HASH CHAIN MATCHING FOR DATA COMPRESSION 审中-公开
公开(公告)号：WO2017052864A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/047856
申请日：2016-08-19
申请人： INTEL CORPORATION
发明人： GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , CUTTER, Daniel F.
IPC分类号： H03M7/30
CPC分类号： H03M7/3086 , H03M7/42
摘要： Example data compression methods disclosed herein include determining a hash chain index corresponding to a first position in an input data buffer based on a group of bytes beginning at a look-ahead offset from the first position. Such disclosed example methods also include, when a hash chain, which is indexed by the hash chain index, satisfies a quality condition, searching the input data buffer at respective adjusted buffer positions corresponding to a set of buffer positions stored in the hash chain being offset by the lookahead offset to find a second data string matching a first data string beginning at the first position in the input data buffer. Such disclosed example methods further include, when the second data string satisfies a length condition, providing a relative position and a length of the second data string to an encoder to output compressed data corresponding to the input data buffer.
摘要翻译：本文公开的示例数据压缩方法包括基于从与第一位置的先行偏移开始的一组字节来确定与输入数据缓冲器中的第一位置相对应的散列链索引。这样公开的示例性方法还包括当由散列链索引索引的散列链满足质量条件时，在对应于存储在散列链中的一组缓冲位置的相应调整的缓冲位置处搜索输入数据缓冲器，通过前视偏移来找到与从输入数据缓冲器中的第一位置开始的第一数据串匹配的第二数据串。这种公开的示例方法还包括当第二数据串满足长度条件时，向编码器提供第二数据串的相对位置和长度以输出对应于输入数据缓冲器的压缩数据。

3. 发明申请

WO2014133705A1 A METHOD, APPARATUS, SYSTEM FOR REPRESENTING, SPECIFYING AND USING DEADLINES 审中-公开
标题翻译：一种用于表示，指定和使用死刑的方法，装置，系统
公开(公告)号：WO2014133705A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/013555
申请日：2014-01-29
申请人： INTEL CORPORATION
发明人： CUTTER, Daniel F. , FANNING, Blaise , NAGARAJAN, Ramadass , IYER, Ravishankar , LE, Quang T. , KOLAGOTLA, Ravi , SCHOINAS, Ioannis T. , NIELL, Jose S.
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在完成存储器请求之前指示最大延迟的期限值。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

4. 发明申请

WO2018125400A1 SYSTEM MEMORY HAVING POINT-TO-POINT LINK THAT TRANSPORTS COMPRESSED TRAFFIC 审中-公开
公开(公告)号：WO2018125400A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/061374
申请日：2017-11-13
申请人： INTEL CORPORATION
发明人： YAP, Kirk S. , CUTTER, Daniel F. , GOPAL, Vinodh
IPC分类号： G06F13/42 , G06F13/16
摘要： An apparatus is described. The apparatus includes a main memory controller having a point-to- point link interface to couple to a point-to-point link. The point-to-point link is to transport system memory traffic between said main memory controller and a main memory. The main memory controller includes at least one of compression logic circuitry to compress write information prior to being transmitted over the link; decompression logic circuitry to decompress read information after being received from the link.

5. 发明申请

WO2017069897A1 DATA COMPRESSION USING ACCELERATOR WITH MULTIPLE SEARCH ENGINES 审中-公开
标题翻译：数据压缩使用加速器与多个搜索引擎
公开(公告)号：WO2017069897A1
公开(公告)日：2017-04-27
申请号：PCT/US2016/052758
申请日：2016-09-21
申请人： INTEL CORPORATION
发明人： GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , CUTTER, Daniel F.
IPC分类号： H03M7/30
CPC分类号： G06F3/0608 , G06F3/064 , G06F3/0656 , G06F3/0661 , G06F3/0685 , G06F12/0292 , G06F12/0638 , G06F12/0684 , G06F12/0868 , G06F12/1018 , H03M7/3086 , H03M7/6011
摘要： In an embodiment, a processor includes hardware processing cores, a cache memory, and a compression accelerator comprising a hash table memory. The compression accelerator is to: determine a hash value for input data to be compressed; read a first plurality of N location values stored in a hash table entry indexed by the hash value; perform a first set of string searches in parallel from a history buffer using the first plurality of N location values stored in the hash table entry; read a second plurality of N location values stored in a first overflow table entry indexed by a first overflow pointer included in the hash table entry; and perform a second set of string searches in parallel from the history buffer using the second plurality of N location values stored in the first overflow table entry. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括硬件处理核，高速缓存存储器以及包括散列表存储器的压缩加速器。压缩加速器将：为要压缩的输入数据确定散列值; 读取存储在由所述散列值索引的散列表项中的第一多个N个位置值; 使用存储在所述散列表条目中的所述第一多个N个位置值，从历史缓冲器并行地执行第一组串行搜索; 读取存储在由所述散列表条目中包括的第一溢出指针索引的第一溢出表条目中的第二多个N位置值; 并且使用存储在第一溢出表项中的第二多个N个位置值从历史缓冲器并行地执行第二组串行搜索。描述并要求保护其他实施例。

6. 发明申请

WO2018017244A1 TECHNOLOGIES FOR HIGH-PERFORMANCE SINGLE-STREAM LZ77 COMPRESSION 审中-公开
标题翻译：高性能单流LZ77压缩技术
公开(公告)号：WO2018017244A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/038323
申请日：2017-06-20
申请人： INTEL CORPORATION
发明人： GOPAL, Vinodh , GUILFORD, James D. , CUTTER, Daniel F. , YAP, Kirk S.
IPC分类号： H03M7/30 , H03M7/40
摘要： Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount, such as eight bytes. The computing device processes multiple chunks in parallel using the index data to generate multiple token streams. The tokens include literal tokens and reference tokens that refer to matching data from earlier in the input data stream. The computing device thus searches for matching data in parallel. The computing device merges the token streams to generate a single output token stream. The computing device may merge a pair of tokens from two different chunks to generate one or more synchronized tokens that are output to the output token stream. Other embodiments are described and claimed.
摘要翻译：用于高性能单流数据压缩的技术包括基于输入数据流更新索引数据结构的计算设备。输入数据流被分成多个块。每个块具有预定的长度，诸如136个字节，并且与前一个块重叠预定量，诸如八个字节。计算设备使用索引数据并行处理多个块以生成多个令牌流。令牌包括文字标记和引用标记，引用来自输入数据流中较早的匹配数据。计算设备因此并行地搜索匹配数据。计算设备合并令牌流以生成单个输出令牌流。计算设备可以合并来自两个不同块的一对令牌，以生成输出到输出令牌流的一个或多个同步令牌。描述并要求保护其他实施例。

7. 发明申请

WO2017053791A1 SYSTEMS, METHODS, AND APPARATUSES FOR COMPRESSION USING HARDWARE AND SOFTWARE 审中-公开
标题翻译：使用硬件和软件进行压缩的系统，方法和装置
公开(公告)号：WO2017053791A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/053433
申请日：2016-09-23
申请人： INTEL CORPORATION
发明人： GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , CUTTER, Daniel F.
IPC分类号： H03M7/30
CPC分类号： H03M7/3082 , H03M7/3086 , H03M7/40
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for compression using hardware and software. Embodiments include compressor hardware to operate on two streams with one of the streams being an offset of the other stream. Additionally, in some embodiments, the output of the compressor hardware is submitted to software for further processing.
摘要翻译：这里详细描述了使用硬件和软件进行压缩的系统，方法和装置的实施例。实施例包括在两个流之间操作的压缩器硬件，其中一个流是另一个流的偏移。另外，在一些实施例中，压缩机硬件的输出被提交给软件进行进一步的处理。

8. 发明申请

WO2014113225A1 ARBITRATING MEMORY ACCESSES VIA A SHARED MEMORY FABRIC 审中-公开
标题翻译：通过一个共享的记忆织物记录存储器
公开(公告)号：WO2014113225A1
公开(公告)日：2014-07-24
申请号：PCT/US2014/010275
申请日：2014-01-06
申请人： INTEL CORPORATION
发明人： CUTTER, Daniel F. , FANNING, Blaise , NAGARAJAN, Ramadass , NIELL, Jose S. , BERNSTEIN, Debra , LIMAYE, Deepak , SCHOINAS, Ioannis T. , IYER, Ravishankar
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/161 , G06F2212/1024 , G06F2213/0064 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

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