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1. 发明申请

WO2012003239A3 AC ADAPTOR MINIMIZATION THROUGH ACTIVE PLATFORM POWER CONSUMPTION MANAGEMENT 审中-公开
标题翻译：通过有源平台功耗管理实现AC适配器最小化
公开(公告)号：WO2012003239A3
公开(公告)日：2012-04-12
申请号：PCT/US2011042449
申请日：2011-06-29
申请人： INTEL CORP , HERMERDING II JAMES G , RODRIGUEZ JORGE P , SRINIVASAN VASUDEVAN
发明人： HERMERDING II JAMES G , RODRIGUEZ JORGE P , SRINIVASAN VASUDEVAN
IPC分类号： G06F1/32 , G06F1/26 , H02J7/00
CPC分类号： H02J7/34 , G06F1/206 , G06F1/26 , G06F1/3234 , H02J7/0068 , Y02D10/16 , Y10T307/625
摘要： Systems and methods of managing platform power consumption may involve determining a power consumption level of a platform based on at least in part a current supplied by an AC adaptor. A power limit of an integrated circuit in the platform can be determined based on at least in part the power consumption level of the platform, wherein the power level may be applied to the integrated circuit.
摘要翻译：管理平台功耗的系统和方法可以包括至少部分地基于由AC适配器提供的电流来确定平台的功率消耗水平。可以至少部分地基于平台的功率消耗水平来确定平台中的集成电路的功率限制，其中功率电平可以被施加到集成电路。

2. 发明申请

WO2014093326A3 METHOD AND APPARATUS FOR MANAGING COMPUTING SYSTEM POWER 审中-公开
标题翻译：用于管理计算系统功率的方法和设备
公开(公告)号：WO2014093326A3
公开(公告)日：2014-12-04
申请号：PCT/US2013074092
申请日：2013-12-10
申请人： INTEL CORP , UAN-ZO-LI ALEXANDER B , RODRIGUEZ JORGE P , LEHWALDER PHILIP R , LEUNG PATRICK K , HERMERDING II JAMES G , SRINIVASAN VASUDEVAN
发明人： UAN-ZO-LI ALEXANDER B , RODRIGUEZ JORGE P , LEHWALDER PHILIP R , LEUNG PATRICK K , HERMERDING II JAMES G , SRINIVASAN VASUDEVAN
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/28 , G06F1/3212 , Y02B60/1285 , Y02B60/1292 , Y02D10/172 , Y02D10/174
摘要： An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.
摘要翻译：一种装置可以包括耦合到一个或多个平台组件的第一电路，第一电路用于接收未滤波的输入电压信号，将未滤波的输入电压信号的第一电压电平与第一参考电压电平进行比较，并且生成控制信号，当所述第一电压电平小于所述第一参考电压电平时，降低所述一个或多个平台组件中的一个或多个平台组件的操作功率。

3. 发明申请

WO0250852A2 CAPACITOR WITH EXTENDED SURFACE LANDS AND METHOD OF FABRICATION THEREFOR 审中-公开
标题翻译：具有扩展表面的电容器及其制造方法
公开(公告)号：WO0250852A2
公开(公告)日：2002-06-27
申请号：PCT/US0144822
申请日：2001-11-27
申请人： INTEL CORP , FIGUEROA DAVID , WALK MICHAEL J , RODRIGUEZ JORGE P , DO HUONG
发明人： FIGUEROA DAVID , WALK MICHAEL J , RODRIGUEZ JORGE P , DO HUONG
IPC分类号： H01G4/252 , H01G20060101 , H01G2/00 , H01G2/06 , H01G2/20 , H01G4/228 , H01L23/52 , H01G
CPC分类号： H01G2/065 , H01L2924/15311
摘要： A capacitor (Figures 6-9) includes one or more extended surface lands (604, 704, 804, 904, Figures 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, Figure 6) of the capacitor or 20% of the length (914, figure 9) of the capacitor. When embedded within an integrated circuit package (1102, Figure 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).
摘要翻译：电容器（图6-9）包括一个或多个延伸的表面焊盘（604,704,804,904，图6-9）。在一个实施例中，每个延伸表面焊盘是在电容器的顶部或底部表面上的焊盘，其具有等于电容器的宽度（图6的614）或者电容器的宽度的至少30％的20％长度（914，图9）。当嵌入集成电路封装（1102，图11）中时，两个或更多个通孔（1112）可以电连接到扩展表面焊盘（1108）。

4. 发明申请

WO02054421A3 MULTIPLE TIER ARRAY CAPACITOR AND METHODS OF FABRICATION THEREFOR 审中-公开
标题翻译：多层阵列电容器及其制造方法
公开(公告)号：WO02054421A3
公开(公告)日：2003-11-06
申请号：PCT/US0144878
申请日：2001-11-28
申请人： INTEL CORP , MOSLEY LARRY E , DO HUONG , FIGUEROA DAVID G , BROWN KENNETH M , CHAKRAVORTY KISHORE K , RODRIGUEZ JORGE P
发明人： MOSLEY LARRY E , DO HUONG , FIGUEROA DAVID G , BROWN KENNETH M , CHAKRAVORTY KISHORE K , RODRIGUEZ JORGE P
IPC分类号： H01G2/06 , H01G4/30 , H01G4/38 , H05K1/00 , H05K1/16
CPC分类号： H01G4/30 , H01L23/642 , H01L2224/16225 , H01L2924/00014 , H05K1/0298 , H05K1/162 , H01L2224/0401
摘要： A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, Figures 3, 12, 13) which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, Figures 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, Figures 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tieres (1310, 1312, Figure 13) are located in a peripheral region (1408, Figure 14) of the capacitor, and one or more other tiers (1380, Figure 13) are located in a peripheral region (1408, Figure 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, Figure 13) of patterned conductive material. The capacitors of the various embodiments can be used as discretedevices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricatad within the housing.
摘要翻译：电容器包括以不同的电感值向负载提供电容的多层（302,304,306,1210,1212,1310,1312,1380，图3,12,13）。每个层包括由介电材料层隔开的图案化导电材料的多层（311-325,1220,1222,1320,1322,1382，图3,12,13）。在一个实施例中，层在垂直方向上堆叠，并且通过延伸穿过层的一些或全部的通孔（330,332,334,1230,1232，图3,12）电连接。在另一个实施例中，一个或多个连接件（1310,1312，图13）位于电容器的外围区域（1408，图14）中，并且一个或多个其它层（1380，图13）位于周边区域（1408，图14）。在该实施例中，中心层和外围层通过图案化导电材料的一个或多个附加层（1370，图13）电连接。各种实施例的电容器可以用作可安装在壳体（例如，封装，插入件，插座或PC板）中或嵌入在壳体（例如，封装，插入件，插座或PC板）中）的隔离装置，或者它们可以整体地装配在壳体内。

5. 发明申请

WO02078054A3 INTEGRATED CIRCUIT PACKAGE WITH A CAPACITOR 审中-公开
标题翻译：集成电路与电容器的封装
公开(公告)号：WO02078054A3
公开(公告)日：2003-09-18
申请号：PCT/US0204144
申请日：2002-02-11
申请人： INTEL CORP , FIGUEROA DAVID G , MALLIK DEBENDRA , RODRIGUEZ JORGE P
发明人： FIGUEROA DAVID G , MALLIK DEBENDRA , RODRIGUEZ JORGE P
IPC分类号： H01L23/12 , H01L21/822 , H01L23/498 , H01L23/64 , H01L27/04 , H05K1/18
CPC分类号： H01L23/49822 , H01L23/642 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/15311 , H01L2924/3011 , H01L2224/0401
摘要： An apparatus includes a package (32)having a first surface (38)and a conductive contact (34)exposed at the first surface. A capacitor (10)is inside the package (32). The capacitor (10)has a first conductive contact (12)exposed at a first surface (24)of the capacitor. The first conductive contact has a first portion (15)spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion (15)of the first conductive contact (12)of the capacitor to the first conductive contact (34)proximate the first surface of the package.
摘要翻译：一种装置包括具有在第一表面处暴露的第一表面（38）和导电接触（34）的封装（32）。电容器（10）在封装（32）内。电容器（10）具有在电容器的第一表面（24）处露出的第一导电接触（12）。第一导电接触件具有横跨电容器的第一表面的宽度的第一部分（15）。电容器的第一表面基本上平行于封装的第一表面。导电路径将电容器的第一导电触头（12）的第一部分（15）连接到靠近封装的第一表面的第一导电触头（34）。

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