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1. 发明申请

WO0115219A3 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT HAVING AT LEAST ONE METALICIZED SURFACE 审中-公开
标题翻译：方法制造集成电路与至少一个金属化
公开(公告)号：WO0115219A3
公开(公告)日：2001-07-19
申请号：PCT/DE0002811
申请日：2000-08-18
申请人： INFINEON TECHNOLOGIES AG , SCHWARZL SIEGFRIED , ENGELHARDT MANFRED , KREUPL FRANZ
发明人： SCHWARZL SIEGFRIED , ENGELHARDT MANFRED , KREUPL FRANZ
IPC分类号： H01L21/28 , H01L21/311 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76807 , H01L21/31144 , H01L21/76813
摘要： The invention relates to the production of a metalicized surface having conductors and contacts wherein dielectric layers are applied to a substrate (4). Contact holes are etched through the two upper-most dielectric layers extending as far as the dielectric layers which lie below. The remaining layer thickness is approximately the same as the thickness of the upper-most layer. Thereafter, trenches for the conductors are selectively etched into the first dielectric layer and the third dielectric layer whose surface is practically laid bare at the same time. After structuring of the first dielectric layer and the third dielectric layer has taken place, contacts and conductors are arranged in the contact holes and conductor trenches.
摘要翻译：以产生具有电介质层施加到基底上（4）引线和接触金属化。有首先通过下面的介电层在顶部两个电介质层，其中，该层的剩余厚度基本上等于最上面Schicknt的厚度的接触孔。随后，Leitungsgrabenätzung选择性到所述第一介电层和第三介电层，其表面的基本上同时暴露发生。第一介电层的结构和第三介电层之后的接触和线接触孔和沟槽中产生。

2. 发明申请

WO02095827A3 METHOD FOR PRODUCING A SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：一种用于生产半导体存储器件
公开(公告)号：WO02095827A3
公开(公告)日：2003-08-21
申请号：PCT/DE0201651
申请日：2002-05-07
申请人： INFINEON TECHNOLOGIES AG , NUETZEL JOACHIM , SCHWARZL SIEGFRIED
发明人： NUETZEL JOACHIM , SCHWARZL SIEGFRIED
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8239 , H01L21/8246 , H01L27/00 , H01L27/22
CPC分类号： H01L27/222
摘要： The invention relates to an especially simple method for producing semiconductor storage devices (1). Said method enables diffusion barriers (30f) to be formed between laterally arranged storage elements (20) by depositing a material region for a first passivation region (30) and by subsequently polishing with a barrier layer on an essentially common level (26a) of the storage elements (20).
摘要翻译：它是呈现的半导体存储器装置的一种特别简单的制造方法（1），其中扩散阻挡层（30F）横向布置的存储元件（20）通过在基本上相同的水平上沉积材料区域用于第一钝化区（30），并通过随后的抛光停止（间 26a）的所述存储器元件被其形成。

3. 发明申请

WO2005116771A3 WAVELENGTH SELECTOR FOR THE SOFT X-RAY RANGE AND THE EXTREME ULTRAVIOLET RANGE 审中-公开
标题翻译：波长软X射线和极紫外范围
公开(公告)号：WO2005116771A3
公开(公告)日：2006-06-08
申请号：PCT/DE2005000973
申请日：2005-05-26
申请人： INFINEON TECHNOLOGIES AG , SCHWARZL SIEGFRIED , WURM STEFAN
发明人： SCHWARZL SIEGFRIED , WURM STEFAN
IPC分类号： G03F7/20
CPC分类号： G03F7/70575
摘要： The invention relates to a wavelength selector for the soft X-ray range and/or the extreme ultraviolet range. Said wavelength selector comprises at least two reflectors that are optically connected in series in such a manner that a beam incident on the first reflector runs in a substantially fixed angular correlation with the beam reflected by the last reflector. At least one of the reflectors (M1, M2, M3, M4) has a wavelength-selective area and the angle of incidence (a, a+?) of at least two of the reflectors (M1, M2, M3, M4) can be modified for the purpose of wavelength selection. The invention provides a wavelength selector for the soft X-ray range that can be used in laboratory conditions and that allows in an inexpensive manner to provide soft X-ray radiation or extreme UV radiation of variable frequency, especially in the wavelength range of 10-15nm. The inventive selector can be easily incorporated into existing laboratory installations.
摘要翻译：本发明涉及一种在软X射线和/或极紫外线区域的波长，所述波长选择器具有被如此光学串联连接的至少两个反射器，其在第一反射器的入射光束的传入从在所述基本固定的角度关系的最后一个反射器反射光束穿过，其中，所述反射器（M1，M2，M3，M4）的至少一种具有波长选择性的区域和发生率的至少两个反射器（M1，M2，M3，M4）的角度（α，α+β）是用于波长选择的变量。本发明解决了在波长范围10-15nm的指定适用于实验室工作波长在软X射线范围内，提供可调谐的软X射线或极紫外辐射，特别的问题，廉价地启用和容易插入到现有的实验设备。

4. 发明申请

WO02071482A2 HOLLOW STRUCTURE IN AN INTEGRATED CIRCUIT AND METHOD FOR PRODUCING SUCH A HOLLOW STRUCTURE IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：中空结构，集成电路和方法HERSETELLEN中空结构，在集成电路
公开(公告)号：WO02071482A2
公开(公告)日：2002-09-12
申请号：PCT/DE0200554
申请日：2002-02-15
申请人： INFINEON TECHNOLOGIES AG , PAMLER WERNER , SCHWARZL SIEGFRIED , GABRIC ZVONIMIR
发明人： PAMLER WERNER , SCHWARZL SIEGFRIED , GABRIC ZVONIMIR
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a hollow structure (100) in an integrated circuit, comprising a first layer (101), a first layer surface (103) and webs (104) disposed thereon one beside the other, said webs including interstices (401), and a second layer (105) and a third layer (106) disposed thereon. The hollow structure further comprises a fourth layer (107) that closes some of the interstices (401), said fourth layer being disposed on the third layer (106) and having a second layer surface (108), the interstices (401) not being closed by the fourth layer (107) being filled with an electrically conducting material.
摘要翻译：在集成电路中的空腔结构（100）具有第一层（101），第一层表面（103）并在此并排腹板（104），其包括间隙（401）和第二层（105）和随后的第三层（106），具有一些间隙（401）最终第四布置在第三层（106）和第二层表面（108）在层（107），并且其中所述第四层的装置（107 ）未完成中间空间（401）填充有导电材料。

5. 发明申请

WO2004109405A2 DEVICE FOR GENERATION OF AND/OR INFLUENCING ELECTROMAGNETIC RADIATION FROM A PLASMA 审中-公开
标题翻译：设备的生产和/或影响等离子体的电磁辐射
公开(公告)号：WO2004109405A2
公开(公告)日：2004-12-16
申请号：PCT/DE2004001132
申请日：2004-05-27
申请人： INFINEON TECHNOLOGIES AG , SCHWARZL SIEGFRIED , WURM STEFAN
发明人： SCHWARZL SIEGFRIED , WURM STEFAN
IPC分类号： G03F7/20
CPC分类号： B82Y10/00 , G03F7/70033 , G03F7/70175 , G03F7/70983
摘要： The invention relates to a device for generation of and/or influencing electromagnetic radiation from a plasma, for the lithographic production of semiconductor elements, in particular, for the generation and/or reflection of EUV-radiation for EUV-lithography. According to the invention, a magnetic means (10) for the generation of at least one inhomogeneous magnetic field (11) is provided as means for the targetted screening of at least one surface of the device (1; 5; 12) and/or another component (5; 12) from the charge carriers in the plasma (3). The service life of the device and/or other components is thus increased.
摘要翻译：本发明涉及一种用于生产和/或用于半导体器件的光刻制造的等离子体的Beinflussung电磁辐射的装置，特别是用于制造和/或EUV辐射的反射的EUV光刻。（5; 112）的装置的至少一个表面上的根据本发明的，用于产生至少一个非均匀磁场（11）的等离子体的电荷载体靶向筛选的装置的磁铁装置（10）（3）。而且/或另一组件（5 ; 12）。以这种方式，该装置和/或其它部件的寿命得以提高。

6. 发明申请

WO02071482A8 HOLLOW STRUCTURE IN AN INTEGRATED CIRCUIT AND METHOD FOR PRODUCING SUCH A HOLLOW STRUCTURE IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：中空结构，集成电路和一种用于生产中空结构在集成电路
公开(公告)号：WO02071482A8
公开(公告)日：2003-08-28
申请号：PCT/DE0200554
申请日：2002-02-15
申请人： INFINEON TECHNOLOGIES AG , PAMLER WERNER , SCHWARZL SIEGFRIED , GABRIC ZVONIMIR
发明人： PAMLER WERNER , SCHWARZL SIEGFRIED , GABRIC ZVONIMIR
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a hollow structure (100) in an integrated circuit, comprising a first layer (101), a first layer surface (103) and webs (104) disposed thereon one beside the other, said webs including interstices (401), and a second layer (105) and a third layer (106) disposed thereon. The hollow structure further comprises a fourth layer (107) that closes some of the interstices (401), said fourth layer being disposed on the third layer (106) and having a second layer surface (108), the interstices (401) not being closed by the fourth layer (107) being filled with an electrically conducting material.
摘要翻译：在集成电路中的空腔结构（100）具有第一层（101），第一层表面（103）并在此并排腹板（104），其包括间隙（401）和第二层（105）和随后的第三层（106），具有一些间隙（401）最终第四布置在第三层（106）和第二层表面（108）在层（107），并且其中所述第四层的装置（107 ）未完成中间空间（401）填充有导电材料。

7. 发明申请

WO02095794A3 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
标题翻译：半导体存储装置及其制造方法
公开(公告)号：WO02095794A3
公开(公告)日：2003-10-16
申请号：PCT/DE0201818
申请日：2002-05-21
申请人： INFINEON TECHNOLOGIES AG , NUETZEL JOACHIM , SCHLOESSER TILL , SCHWARZL SIEGFRIED , WURM STEFAN
发明人： NUETZEL JOACHIM , SCHLOESSER TILL , SCHWARZL SIEGFRIED , WURM STEFAN
IPC分类号： H01L27/10 , H01L20060101 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
CPC分类号： H01L27/222 , B82Y10/00
摘要： The aim of the invention is to integrate a capacitor device (40) in the area of a semiconductor memory device while using particularly few process steps. To this end, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) to be provided are to be structured directly underneath or directly above the material area (30) that accommodates the memory elements (20). These electrode devices are to be structured so that at least one portion of the material area (30) that accommodates the memory elements (20) functions as a part of the respective dielectric (45) between the electrode devices (43, 44).
摘要翻译：用于在具有特别少的工艺步骤的半导体存储器件的区域中的积分电容器装置的提出，要被提供的电容器装置的正下方或正上方的下电极装置和的上部电极装置具有材料区auzubilden存储器元件，使得由至少具有存储器元件材料区域的一部分作用在电极装置之间的各个介质的至少一部分。

8. 发明申请

WO03034436A3 SEMICONDUCTOR STORAGE UNIT PROVIDED WITH INTERSECTING WORD AND BIT LINES WHEREON ARE ARRANGED MAGNETORESISTIVE MEMORY CELLS 审中-公开
标题翻译：半导体存储器具有交叉字和位线，其中磁阻存储器单元安排
公开(公告)号：WO03034436A3
公开(公告)日：2003-08-14
申请号：PCT/DE0203491
申请日：2002-09-17
申请人： INFINEON TECHNOLOGIES AG , SCHWARZL SIEGFRIED
发明人： SCHWARZL SIEGFRIED
IPC分类号： G11C11/15 , G11C11/16 , G11C29/04 , G11C29/56
CPC分类号： G11C11/16 , G11C11/15
摘要： The invention concerns a semiconductor storage unit in the memory field (2) of which, storage elements, and more precisely memory cells (1) with magnetoresitive effect are characterized by a hard magnetic memory layer (10) and a soft magnetic sensor layer (11) whereof the light magnetization axes (30, 31) intersect. The magnetization axis (30) of the hard magnetic layer (10) is parallel to the line adjacent thereto, for example the bit line (9), and the magnetization axis (31) is parallel to the line which is adjacent thereto, for example, the word line (8). Preferably, said axes with their respective parallel line are substantially perpendicular one above the other. An alternating voltage source (51), or more precisely an alternating current source (50) enables application of a voltage signal or more precisely a current signal on the selected line, the word line (8) for example. The magnetization direction (21) of the soft magnetic layer (11) is thus deflected sinusoidally from the light magnetization axis (31). Besides the applied signal, the magnetoresistive resistor of the memory cell is also thereby modified. Depending on the magnetization direction (20) of the hard magnetic layer (10), the signal is phase- or phase-shifted modulated in similar or opposite by the variable resistor, such that a direct voltage accompanied by a polarity sign and a first harmonic wave, for example, can be detected as components of the resulting measuring signal. The polarity sign delivers memory data.
摘要翻译：在半导体存储器中（2）的存储单元阵列，由硬磁性存储层（10）和一个软磁性传感器层（11）的存储元件或存储器单元（1）与磁阻效应，其特征在于，其易磁化轴（30，31）相交。硬磁层（10）的磁化强度（30）的轴线平行于连接到它线，如位线（9），和磁化轴（31）平行于连接到其线，如该字线（8）。优选地，其中的轴线与相应的平行线基本上垂直相关。在每种情况下所选择的线，例如，字线（8）的电压或电流信号的特征在于AC（51）和交流电源（50）。软磁性层（11）的磁化方向（21）从而从正弦的易磁化轴（31）偏转。除了外加信号的特征还在于所述的存储器单元的变化的磁阻效应的阻力。取决于硬磁层的磁化强度（20）（10）的方向是在由可变电阻器或反相调制的相同的信号，使得从得到的测量信号，例如部件一个签名的直流电压，并且可以检测一个二次谐波。符号提供了存储信息。

9. 发明申请

WO0010172A3 STORAGE CELL ARRAY AND CORRESPONDING PRODUCTION METHOD 审中-公开
标题翻译：存储器单元装置和方法及其
公开(公告)号：WO0010172A3
公开(公告)日：2000-06-08
申请号：PCT/DE9902402
申请日：1999-08-02
申请人： SIEMENS AG , SCHWARZL SIEGFRIED
发明人： SCHWARZL SIEGFRIED
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： G11C11/16 , B82Y10/00 , G11C11/14 , H01L27/222
摘要： In a storage cell array, a first and a second line are provided, on whose crossing point a storage element with magnetoresistive effect is disposed. A yoke is provided, surrounding one of the lines and containing magnetizable material with a permeability of at least 10. The yoke is disposed in such a way that a magnetic flow is closed substantially through the storage element.
摘要翻译：在一个存储单元阵列，第一和第二线设置，在它们的交叉点与磁阻效应的存储元件设置。这是一个磁轭设置，包围在每种情况下的线路之一和含有可磁化材料与至少10度的渗透性。磁轭被布置成使得磁通由存储器元件上方的磁轭基本闭合。

10. 发明申请

WO0004555A2 STORAGE CELL SYSTEM IN WHICH AN ELECTRIC RESISTANCE OF A STORAGE ELEMENT REPRESENTS AN INFORMATION UNIT AND CAN BE INFLUENCED BY A MAGNETIC FIELD, AND METHOD FOR PRODUCING SAME 审中-公开
标题翻译： IN MEMORY元素释放的电阻电池结构代表并受磁场的影响，其制造方法
公开(公告)号：WO0004555A2
公开(公告)日：2000-01-27
申请号：PCT/DE9901958
申请日：1999-07-01
申请人： SIEMENS AG , GOEBEL BERND , JACOBS HERMANN , SCHWARZL SIEGFRIED , BERTAGNOLLI EMMERICH
发明人： GOEBEL BERND , JACOBS HERMANN , SCHWARZL SIEGFRIED , BERTAGNOLLI EMMERICH
IPC分类号： G11C11/14 , G11C11/15 , H01L21/8246 , H01L27/105 , H01L27/22 , G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15
摘要： According to the invention a storage cell comprises a storage element whose electric resistance represents an information unit and can be influenced by a magnetic field as well as a transistor which when the information is read out allows for the corresponding storage cell to be selected from among the storage cells. To write the information unit the invention provides for a write line (SLa) and a bit line (Ba) which intersect in the area of the storage element and are able to generate the magnetic field. The storage element and the transistor can be connected in series. The storage cell can be mounted between the bit line (Ba) and a shared voltage supply connection for the storage cells. The storage cell can be mounted between the bit line (Ba) and the write line (SLa) and the write line (SLa) can coincide with a gate line (GLa) which controls the transistor. The transistor can be configured in a planar or vertical manner. The storage element and the transistor can be positioned next to or on top of each other.
摘要翻译：存储器单元包括其电阻表示信息并且可受磁场影响的存储器元件和晶体管，其中晶体管在读出信息时允许选择存储器单元中的相关存储器单元。为了写入信息，提供写线（SLa）和位线（Ba），其在存储元件的区域中相交并且可以产生磁场。存储元件和晶体管可以串联连接。存储器单元可以连接在位线（Ba）和存储器单元公共的电压连接之间。存储器单元可以连接在位线（Ba）和写入线（SLa）之间。写入线（SLa）可以与驱动晶体管的栅极线（GLa）重合。晶体管可以是平面的或垂直的。存储器元件和晶体管可以并排或者一个在另一个之上地布置。

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