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1. 发明申请

WO03090257A2 METHOD FOR THE PRODUCTION OF THIN METAL-CONTAINING LAYERS HAVING LOW ELECTRICAL RESISTANCE 审中-公开
标题翻译：方法用于制造具有低电阻金属薄层
公开(公告)号：WO03090257A2
公开(公告)日：2003-10-30
申请号：PCT/DE0301205
申请日：2003-04-10
申请人： INFINEON TECHNOLOGIES AG , BARTH HANS-JOACHIM , TEWS HELMUT
发明人： BARTH HANS-JOACHIM , TEWS HELMUT
IPC分类号： C25D5/50 , C25D7/12 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76886
摘要： The invention relates to a method for producing thin metal-containing layers (5C) having low electrical resistance, according to which a metal-containing initial layer (5A) having a first grain size is configured on a carrier material (2) in a first step. A locally restricted heated area (W) is then created and moved within the metal-containing initial layer (5A) in such a way that the metal-containing initial layer (5A) is recrystallized so as to create the metal-containing layer (5C) having a second grain size which is enlarged to the first grain size, whereby a metal-containing layer having improved electrical properties is obtained.
摘要翻译：本发明涉及一种用于制造含有金属的薄层（5C）具有低的电阻，其特征在于，最初具有在载体材料（2）的第一粒度前体层（5A）含金属的形成的方法。随后，以这样的方式产生在含有金属的起始层（5A）局部限制热范围（W）和移动，使得用于制备含有金属的层（5C）的含金属的输出层（5A）的再结晶具有增加至所述第一粒度的第二粒度进行。以这种方式，得到具有改善的电性能的含金属层。

2. 发明申请

WO03090257B1 METHOD FOR THE PRODUCTION OF THIN METAL-CONTAINING LAYERS HAVING LOW ELECTRICAL RESISTANCE 审中-公开
标题翻译：生产具有低电阻的薄含金属层的方法
公开(公告)号：WO03090257B1
公开(公告)日：2004-03-04
申请号：PCT/DE0301205
申请日：2003-04-10
申请人： INFINEON TECHNOLOGIES AG , BARTH HANS-JOACHIM , TEWS HELMUT
发明人： BARTH HANS-JOACHIM , TEWS HELMUT
IPC分类号： C25D5/50 , C25D7/12 , H01L21/28 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/76886
摘要： The invention relates to a method for producing thin metal-containing layers (5C) having low electrical resistance, according to which a metal-containing initial layer (5A) having a first grain size is configured on a carrier material (2) in a first step. A locally restricted heated area (W) is then created and moved within the metal-containing initial layer (5A) in such a way that the metal-containing initial layer (5A) is recrystallized so as to create the metal-containing layer (5C) having a second grain size which is enlarged to the first grain size, whereby a metal-containing layer having improved electrical properties is obtained.
摘要翻译：本发明涉及一种用于制造含有金属的薄层（5C）具有低的电阻，其特征在于，最初具有在载体材料（2）的第一粒度前体层（5A）含金属的形成的方法。随后，以这样的方式产生在含有金属的起始层（5A）局部限制热范围（W）和移动，使得用于制备含有金属的层（5C）的含金属的输出层（5A）的再结晶具有增加至所述第一粒度的第二粒度进行。以这种方式，具有改善的电特性的含金属层。

3. 发明申请

WO2004064160A2 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT ARRANGEMENT, IN PARTICULAR COMPRISING A CAPACITOR ASSEMBLY, IN ADDITION TO AN INTEGRATED CIRCUIT ARRANGEMENT 审中-公开
标题翻译：方法制造集成电路，尤其是电容器装置及集成电路
公开(公告)号：WO2004064160A2
公开(公告)日：2004-07-29
申请号：PCT/EP0314974
申请日：2003-12-31
申请人： INFINEON TECHNOLOGIES AG , BARTH HANS-JOACHIM , HOLZ JUERGEN
发明人： BARTH HANS-JOACHIM , HOLZ JUERGEN
IPC分类号： H01L23/522 , H01L23/532 , H01L27/08
CPC分类号： H01L23/5223 , H01L23/53238 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/48463 , H01L2924/14 , H01L2924/00
摘要： The invention relates to a method for producing an integrated circuit arrangement (100) comprising a capacitor (112). A dielectric layer (160) is structured with the aid of a hard mask during a two-stage etching process. The hard mask is subsequently removed if it is an electrically insulating hard mask. If the latter is an electrically conductive hard mask, parts of said mask can remain in the circuit arrangement (100). The integrated circuit arrangement can thus be produced without complex cleaning steps and in addition, the quality of the dielectric in the capacitor is extremely high.
摘要翻译：将说明制造集成电路装置（100）包括一个电容器（112）的方法。介电层（160）是通过两步蚀刻工艺的装置和由硬掩模的装置图案化。硬掩模是在电绝缘硬掩模的情况下除去。在电路装置（100）中的硬掩模的导电硬掩模部分的情况下，可以保持。该集成电路可以毫不复杂的纯化步骤来制备。在电容器中的电介质的质量也很高。

4. 发明申请

WO2004001842A2 LAYER ASSEMBLY AND METHOD FOR PRODUCING A LAYER ASSEMBLY 审中-公开
标题翻译：层及其制造方法的层结构
公开(公告)号：WO2004001842A2
公开(公告)日：2003-12-31
申请号：PCT/DE0301827
申请日：2003-06-03
申请人： INFINEON TECHNOLOGIES AG , BARTH HANS-JOACHIM , SEZI RECAI
发明人： BARTH HANS-JOACHIM , SEZI RECAI
IPC分类号： H01L21/312 , H01L21/768 , H01L23/522 , H01L21/316
CPC分类号： H01L21/768 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a layer assembly and to a method for producing a layer assembly. This layer assembly comprises a layer that is placed on a substrate. Said layer comprises a first partial region, which is made of a decomposable material, and an adjacent second partial region with a useful structure made of a non-decomposable material. The layer assembly also has a top layer which is arranged on the layer made of a decomposable material and the useful structure. The layer assembly is designed so that the decomposable material can be removed from the layer assembly.
摘要翻译：本发明涉及一种层排列和用于制造层结构的方法。层布置被设置在具有由可分解材料的和用非可降解材料的一种有用的结构旁边的第二部分区域布置在第一部分上的基底层上。此外，该层布置具有分解材料的层和所述有用结构上的覆盖层，其中所述层布置被设置为使得所述可降解材料由层组装的是可移除的。

5. 发明申请

WO03041144A3 METHOD FOR PRODUCING THIN METAL-CONTAINING LAYERS HAVING A LOW ELECTRICAL RESISTANCE 审中-公开
标题翻译：方法用于制造具有低电阻金属薄层
公开(公告)号：WO03041144A3
公开(公告)日：2003-09-18
申请号：PCT/DE0203344
申请日：2002-09-09
申请人： INFINEON TECHNOLOGIES AG , BARTH HANS-JOACHIM
发明人： BARTH HANS-JOACHIM
IPC分类号： H01L21/768
CPC分类号： H01L21/76838
摘要： The invention relates to a method for producing thin metal-containing layers having a low electrical resistance during which a metal-containing layer (5') having a first grain size is firstly formed until it has a first thickness (d1). Once this thickness (d1) is attained, a recrystallization is subsequently carried out in order to produce a metal-containing layer (5'') having an increased grain size. Afterwards, the metal-containing layer (5'') having the increased grain size is thinned until it has a desired target thickness (d2) whereby obtaining a very thin metal-containing layer having a reduced electrical resistance.
摘要翻译：本发明涉及用于生产薄膜具有低电阻，最初是一个含金属层（5“）含金属的与第一粒度达一第一厚度（d1）的形成，并且然后在该厚度（d1）的再结晶对生成的方法含金属的层（5'）是具有增加的粒度进行。最后，将含有金属的层（5“”）与所述放大的晶粒尺寸至期望的目标厚度（d2）的减薄，从而获得具有进一步降低的电阻的非常薄的含金属层。

6. 发明申请

WO0184604A3 METHOD FOR PRODUCING AN INTEGRATED CAPACITOR 审中-公开
标题翻译：方法用于制造集成电容器
公开(公告)号：WO0184604A3
公开(公告)日：2002-02-28
申请号：PCT/EP0104525
申请日：2001-04-20
申请人： INFINEON TECHNOLOGIES AG , AUGUSTIN ANDREAS , KLEIN WOLFGANG , BARTH HANS JOACHIM
发明人： AUGUSTIN ANDREAS , KLEIN WOLFGANG , BARTH HANS-JOACHIM
IPC分类号： H01L21/02 , H01L21/768
CPC分类号： H01L28/75 , H01L21/76838 , H01L28/55 , H01L28/82
摘要： The invention relates to a method for producing an integrated capacitor consisting of the following steps: namely, the formation of a structured metal layer (1) on a supporting layer (2); covering the structured metal layer (1) and the supporting layer (2) with a thick dielectric layer (3); carrying out a local etching through the thick dielectric layer (3) until reaching the structured first metal layer (1) in order to form an etched opening having a lateral wall surface (4) and a bottom surface (5), which is formed by the exposed surface of the structured first metal layer (1); precipitating a first conductive layer (7) on the formed bottom surface (5) and on the thick dielectric layer (3); precipitating a thin dielectric layer (8) on the first conductive layer (7); precipitating a second conductive layer (9) on the thin dielectric layer (8), and; forming a structured second metal layer (10) on the second conductive layer (9).
摘要翻译：一种用于制造集成电容器，其包括以下步骤，即载体层（2）上形成的图案化金属层（1）的方法; 涂覆所述图案化金属层（1）和所述载体层（2）用厚dielekrischen层（3）; （1）形成通过所述厚电介质层（3），以用于形成具有侧壁表面的蚀刻孔图案化第一金属层（1）本地Hindurchätzen（4）和（5）通过所述结构化第一金属层的暴露表面的基座会; （7）形成的底表面（5）和厚的电介质层（3）上沉积第一导电层; 在第一导电层上沉积一薄介电层（8）（7）; 薄介电层上沉积一第二导电层（9）（8）; 和所述第二导电层上形成图案化的第二金属层（10）（9）。

7. 发明申请

WO2004027865A3 SUPPORT STRUCTURES FOR WIREBOND REGIONS OF CONTACT PADS OVER LOW MODULUS MATERIALS 审中-公开
标题翻译：用于低模量材料的接触焊片线区的支撑结构
公开(公告)号：WO2004027865A3
公开(公告)日：2004-07-15
申请号：PCT/EP0310401
申请日：2003-09-18
申请人： INFINEON TECHNOLOGIES AG , IBM
发明人： ANDERSON DAVID , BARTH HANS-JOACHIM , BURRELL LLOYD G , CHAN JOSEPH , CRABBE EMMANUEL F , KEMERER DOUGLAS W , NYE ILL HENRY A
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/05 , H01L24/06 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05546 , H01L2224/05553 , H01L2224/05599 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2224/48624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01061 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlaying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).
摘要翻译：一种半导体器件（200），其具有在接触焊盘（204）的焊线区（214）下方的支撑结构（218,226,236）及其形成方法。低模量介电层（216,222,232）设置在工件（212）上方。在低模量介电层（216,222,232）中形成支撑结构（218,226,236），并且在支撑结构（218,226,236）之间形成支撑通孔（224,234）。高模量电介质膜（220,230）设置在每个低模量电介质层（216,222,232）之间，并且高模量电介质层（256）设置在顶部低模量电介质层（232）之上。接触垫（204）形成在高模量电介质层（256）中。在低模量介电层（232）内的每个支撑通孔（234）位于底部低模量介电层（222）中的支撑通孔（224）的正上方，以在低模量介电层（222）内形成多个通孔支撑堆叠 216，222，232）。

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