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    • 8. 发明申请
    • ASYMMETRIC LANES IN POINT-TO-POINT INTERCONNECT
    • 点对点互连中的不对称局域网
    • WO2018000406A1
    • 2018-01-04
    • PCT/CN2016/088084
    • 2016-07-01
    • INTEL CORPORATIONLI, ZhimingRUAN, XingpingHU, XiaoTRAUSCH, TerrenceZHOU, XiangYAN, Jie
    • LI, ZhimingRUAN, XingpingHU, XiaoTRAUSCH, TerrenceZHOU, XiangYAN, JiePEBLY, Robert
    • G06F13/14
    • A system includes a host processor (105) and a peripheral device (708). The host processor(105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.
    • 系统包括主处理器(105)和外围设备(708)。 主机处理器(105)通过外围组件互连快速(PCIe)兼容链路耦合到外围设备(708)。 外围设备(708)可以包括逻辑电路,用于基于使用该设备和主处理器(105)的应用来识别应用所使用的读写比; 并将读写比提供给主处理器(105)。 所述主处理器(105)包括逻辑电路,所述逻辑电路用于通过外围组件互连快速(PCIe)兼容链路向与所述硬件处理器通信的设备发送命令信号,所述命令信号指示要接收(RX)的传输(TX) 通道比率,TX通道与RX通道比率对应于由外围设备(708)识别的读写比率; 并收到设备能够支持不对称TX和RX比率的指示。