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    • 3. 发明申请
    • COMPACT 3-PORT ORTHOGONALLY POLARIZED MIMO ANTENNAS
    • 紧凑的3端口正交偏振MIMO天线
    • WO2009050596A3
    • 2009-10-22
    • PCT/IB2008003850
    • 2008-10-06
    • UNIV HONG KONG SCIENCE & TECHNCHIU CHI YUKYAN JIE BANGMURCH ROSS DAVID
    • CHIU CHI YUKYAN JIE BANGMURCH ROSS DAVID
    • H04J1/00
    • H01Q1/38H01Q9/16H01Q13/106H01Q21/24H01Q25/00
    • Generalized non-limiting embodiments include employing a dipole antenna and/or a half slot antenna. Each of the antennas constitutes three mutually perpendicular radiating elements to achieve good isolation and low antenna signal correlation between the three ports. In one generalized non-limiting embodiment the antennas are fabricated on FR-4 epoxy boards. Experimental results show that the antennas resonate a reasonable frequency and have a desired mutual coupling. In addition experimental results for the diversity performance and the MIMO channel capacity are also provided for these antennas and these results show that the herein described antennas offer good diversity gain and the channel capacity can be increased by as much as three times by using these antennas over conventional antennas.
    • 广义的非限制性实施例包括采用偶极天线和/或半缝隙天线。 每个天线构成三个相互垂直的辐射元件,以实现三个端口之间的良好隔离和低天线信号相关。 在一个广义的非限制性实施例中,天线被制造在FR-4环氧树脂板上。 实验结果表明,天线谐振频率合理,具有理想的互耦。 此外,还为这些天线提供了分集性能和MIMO信道容量的实验结果,并且这些结果表明,本文描述的天线提供良好的分集增益,并且可以通过使用这些天线将信道容量增加多达三倍 常规天线。
    • 10. 发明申请
    • ASYMMETRIC LANES IN POINT-TO-POINT INTERCONNECT
    • 点对点互连中的不对称局域网
    • WO2018000406A1
    • 2018-01-04
    • PCT/CN2016/088084
    • 2016-07-01
    • INTEL CORPORATIONLI, ZhimingRUAN, XingpingHU, XiaoTRAUSCH, TerrenceZHOU, XiangYAN, Jie
    • LI, ZhimingRUAN, XingpingHU, XiaoTRAUSCH, TerrenceZHOU, XiangYAN, JiePEBLY, Robert
    • G06F13/14
    • A system includes a host processor (105) and a peripheral device (708). The host processor(105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.
    • 系统包括主处理器(105)和外围设备(708)。 主机处理器(105)通过外围组件互连快速(PCIe)兼容链路耦合到外围设备(708)。 外围设备(708)可以包括逻辑电路,用于基于使用该设备和主处理器(105)的应用来识别应用所使用的读写比; 并将读写比提供给主处理器(105)。 所述主处理器(105)包括逻辑电路,所述逻辑电路用于通过外围组件互连快速(PCIe)兼容链路向与所述硬件处理器通信的设备发送命令信号,所述命令信号指示要接收(RX)的传输(TX) 通道比率,TX通道与RX通道比率对应于由外围设备(708)识别的读写比率; 并收到设备能够支持不对称TX和RX比率的指示。