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1. 发明申请

WO2005086957A3 HIGHLY LINEAR VARIABLE GAIN AMPLIFIER 审中-公开
标题翻译：高线性可变增益放大器
公开(公告)号：WO2005086957A3
公开(公告)日：2006-11-09
申请号：PCT/US2005008197
申请日：2005-03-10
申请人： GCT SEMICONDUCTOR INC , PARK JOONBAE , LEE SEUNG-WOOK , LEE JEONG-WOO , LEE KYEONGHO
发明人： PARK JOONBAE , LEE SEUNG-WOOK , LEE JEONG-WOO , LEE KYEONGHO
IPC分类号： H03F3/45 , H03F3/21
CPC分类号： H03F3/211 , H03F3/45475 , H03F3/45659 , H03F2203/45136 , H03F2203/45138 , H03F2203/45166 , H03F2203/45168 , H03F2203/45434 , H03F2203/45522 , H03F2203/45591
摘要： A variable-gain amplifier circuit uses a pair of single-ended operational amplifiers (100, 110) to amplify complementary portions of a differential input signal (IN, INB). By using two single-ended amplifiers (100, 110) instead of a single differential amplifier, linearity is significantly improved. In addition, common mode feedback circuitry is eliminated along with harmonic distortion and other forms of noise which tend to negative affect the quality of the signal output from the circuit.
摘要翻译：可变增益放大器电路使用一对单端运算放大器（100,110）来放大差分输入信号（IN，INB）的互补部分。通过使用两个单端放大器（100,110）代替单个差分放大器，线性度显着提高。此外，消除共模反馈电路以及谐波失真和其它形式的噪声，这些噪声倾向于负面影响从电路输出的信号的质量。

2. 发明申请

WO2006036749A3 APPARATUS AND METHOD OF OSCILLATING WIDEBAND FREQUENCY 审中-公开
标题翻译：振荡频率的装置和方法
公开(公告)号：WO2006036749A3
公开(公告)日：2006-09-28
申请号：PCT/US2005034021
申请日：2005-09-21
申请人： GCT SEMICONDUCTOR INC , PARK JOONBAE , LEE SEUNG-WOOK , LEE JEONG-WOO , LEE KYEONGHO
发明人： PARK JOONBAE , LEE SEUNG-WOOK , LEE JEONG-WOO , LEE KYEONGHO
IPC分类号： H03L7/08
CPC分类号： H03L7/113 , H03L7/087 , H03L7/10 , H03L7/187
摘要： An apparatus for oscillating a frequency, which comprises a phase lock loop, see fig. 5, a variable frequency divider() is shown, that divides a first frequency (Fout) signal by a division ratio to generate a second frequency signal, this based on a comparison of reference frequency clock input (Fref) and feedback input to phase/frequency detector (510). A charge pump (520) and loop filter (530) are shown with a divider (550) that divides the second frequency signal (355) to allow the correct feedback frequency to be realized. The VCO (540) inherently has a resonant circuit including the capacitors to be selected and a corresponding control voltage to set the frequency of operation as well as an active circuit (320) for proper gain.
摘要翻译：用于振荡频率的装置，其包括锁相环，参见图1。如图5所示，示出了可变分频器（），其将第一频率（Fout）信号除以分频比以产生第二频率信号，这是基于参考频率时钟输入（Fref）和反相输入到相位/ 频率检测器（510）。示出了电荷泵（520）和环路滤波器（530），其具有分频器（550），其划分第二频率信号（355）以允许实现正确的反馈频率。 VCO（540）固有地具有包括要选择的电容器的谐振电路和用于设置操作频率的相应控制电压以及用于适当增益的有源电路（320）。

3. 发明申请

WO2006055821A3 AN INTEGRATED WIRELESS RECEIVER AND A WIRELESS RECEIVING METHOD THEREOF 审中-公开
标题翻译：一体化无线接收机及其无线接收方法
公开(公告)号：WO2006055821A3
公开(公告)日：2006-08-24
申请号：PCT/US2005041922
申请日：2005-11-18
申请人： GCT SEMICONDUCTOR INC , PARK JOONBAE , LEE SEUNG-WOOK , LEE JEONG-WOO , LEE KYEONGHO
发明人： PARK JOONBAE , LEE SEUNG-WOOK , LEE JEONG-WOO , LEE KYEONGHO
IPC分类号： H04B1/04
CPC分类号： H04B1/26
摘要： A wireless receiver and a wireless receiving method are provided wherein a frequency of a radio frequency (RF) is down-converted into a frequency of a substantially zero intermediate frequency (IF) signal or a substantially low IF signal. The down-converted signal may be filtered by an integrated filter having a low quality factor and then up-converted again into a particular IF signal, thereby integrating an external element. For example, a receiving device may receive a RF signal in a required band. A frequency down-converting device may down-convert a frequency so that a center frequency of the RF signal becomes zero. A channel select filtering device may select a required channel from the signals whose frequency is down-converted. An IF signal converting device may up-convert a frequency of the channel selected signal into a required IF. An IF processing device may extract a baseband signal after the converted IF signal is inputted and processed. An amplifying device may amplify a signal with a gain required in a process of converting a frequency.
摘要翻译：提供了一种无线接收机和无线接收方法，其中射频（RF）的频率被下变频成基本为零的中频（IF）信号或基本上低的IF信号的频率。下变频信号可以由具有低质量因子的积分滤波器滤波，然后再次上变频成特定的IF信号，从而整合外部元件。例如，接收设备可以接收所需频带中的RF信号。降频转换装置可以降频转换频率，使得RF信号的中心频率变为零。频道选择滤波装置可以从频率被下变频的信号中选择所需频道。 IF信号转换装置可以将频道选择信号的频率上变频成所需的IF。 IF处理装置可以在转换的IF信号被输入和处理之后提取基带信号。放大装置可以放大具有在转换频率的过程中所需的增益的信号。

4. 发明申请

WO2005022933A3 SYSTEM AND METHOD FOR FILTERING SIGNALS IN A TRANSCEIVER 审中-公开
标题翻译：用于在收发器中过滤信号的系统和方法
公开(公告)号：WO2005022933A3
公开(公告)日：2005-08-11
申请号：PCT/US2004027799
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR INC , JEON YOUNG-DEUK , LEE SEUNG-WOOK , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
发明人： JEON YOUNG-DEUK , LEE SEUNG-WOOK , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H04B1/38
CPC分类号： H04B1/1027 , H03H11/1252 , H03H11/1291 , H03J1/0008 , H04B1/44
摘要： A system and method for filtering signals in a communications system reduces hardware and chip size requirements by selectively connecting a filter along transmitter and receiver paths of a transceiver. In operation, a controller generated signals for connecting the filter along the transmitter path when the transceiver is in transmitter mode and for connecting the filter along the receiver path when the transmitter is in receiver mode. The controller then generates additional signals for setting one or more parameters of the filter based on the path connected, or put differently based on the operational mode of the transceiver. In a variation, the controller sets the parameters of additional elements coupled to the filter as a way of further controlling processing of the transmitter and receiver signals.
摘要翻译：用于对通信系统中的信号进行滤波的系统和方法通过沿收发器的发射机和接收机路径选择性地连接滤波器来降低硬件和芯片尺寸的要求。在操作中，当收发器处于发射机模式时，控制器产生用于沿着发射机路径连接滤波器的信号，并且当发射机处于接收机模式时，控制器沿着接收机路径连接滤波器。然后，控制器产生附加信号，用于基于连接的路径设置滤波器的一个或多个参数，或者基于收发器的操作模式进行不同的设置。在一个变型中，控制器设置耦合到滤波器的附加元件的参数作为进一步控制发射机和接收机信号的处理的一种方式。

5. 发明申请

WO2005022599A3 INTEGRATED CIRCUIT PACKAGE HAVING INDUCTANCE LOOP FORMED FROM SAME-PIN-TO-SAME-BONDING-PAD STRUCTURE 审中-公开
标题翻译：具有从同一个针对相同结构的结构形成的电感环的集成电路封装
公开(公告)号：WO2005022599A3
公开(公告)日：2006-11-02
申请号：PCT/US2004027855
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR INC , KOO YIDO , HUH HYUNGKI , LEE KANG YOON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
发明人： KOO YIDO , HUH HYUNGKI , LEE KANG YOON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H01L29/00 , H01L20060101 , H01L23/02 , H01L23/38 , H01L23/498 , H01L23/52 , H01L23/64 , H01L29/40 , H03B5/12
CPC分类号： H01L23/642 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.
摘要翻译：集成电路封装包括由接合线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感环路。在一个实施例中，电感环由将集成电路芯片上的焊盘连接到封装的I / O引脚的第一布线和将相同的焊盘连接到同一引脚的第二布线形成。通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。

6. 发明申请

WO2004040898A3 SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT 审中-公开
标题翻译：用于抑制锁相环电路中的噪声的系统和方法
公开(公告)号：WO2004040898A3
公开(公告)日：2004-09-02
申请号：PCT/US0333709
申请日：2003-10-23
申请人： GCT SEMICONDUCTOR INC , AHN YOUNGHO , SONG EUNSEOK , KOO YIDO , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
发明人： AHN YOUNGHO , SONG EUNSEOK , KOO YIDO , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H03L7/197 , H03L7/06
CPC分类号： H03L7/1978
摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.
摘要翻译：用于改善频率发生器的信噪比的系统和方法抑制了由于内部发生器电路中的失配而产生的相位噪声和噪声。这是利用调制方案实现的，该调制方案将发生器的环路带宽之外的寄生噪声信号移位。当以这种方式移动时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全移除或以任何期望的程度移除。在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。在另一个实施例中，输入到锁相环中的参考信号被调制以实现噪声抑制。在另一个实施例中，上述形式的调制被组合以实现期望的频移。通过这些调制技术，频率发生器的信噪比可以显着提高，同时实现更快的锁定时间。

7. 发明申请

WO2006039187A3 SIGMA-DELTA BASED PHASE LOCK LOOP 审中-公开
标题翻译：基于SIGMA-DELTA的相位锁定环
公开(公告)号：WO2006039187A3
公开(公告)日：2007-01-18
申请号：PCT/US2005034018
申请日：2005-09-21
申请人： GCT SEMICONDUCTOR INC , KOO YIDO , AHN YOUNGHO , SONG EUNSEOK , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
发明人： KOO YIDO , AHN YOUNGHO , SONG EUNSEOK , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H03D3/24
CPC分类号： H03L7/0895 , H03L7/1976
摘要： A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PDF to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.
摘要翻译：提供了一种基于Σ-Δ的锁相环装置，其包括相位频率检测器（PFD），电荷泵和压控振荡器。 PDF接收参考信号和反馈信号，并且基于参考信号和反馈信号的比较来输出信号。电荷泵根据PFD的输出信号输出电荷。电荷泵包括施加固定电流量的第一电流源和第二电流源以施加可变量的电流。压控振荡器根据来自电荷泵的接收电荷输出时钟信号。

8. 发明申请

WO2005022597A3 INTEGRATED CIRCUIT PACKAGE HAVING AN INDUCTANCE LOOP FORMED FROM A MULTI-LOOP CONFIGURATION 审中-公开
标题翻译：集成电路封装具有由多环路配置形成的电感环路
公开(公告)号：WO2005022597A3
公开(公告)日：2005-08-04
申请号：PCT/US2004027797
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR INC , KOO YIDO , HUH HYUNGKI , LEE KANG YOON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
发明人： KOO YIDO , HUH HYUNGKI , LEE KANG YOON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H01L20060101 , H01L23/64 , H01L29/00
CPC分类号： H01L23/642 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01043 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.
摘要翻译：集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。在一个实施例中，电感回路由第一和第二导线形成，第一和第二导线将集成电路芯片上的第一焊盘连接到封装的第一I / O管脚，以及第三和第四导线连接芯片上的第二焊盘到封装的第二个I / O引脚。为了完成电感回路，第一和第二I / O引脚通过引脚之间的第三导体连接。第三导体可以包括一个或多个键合线，并且I / O引脚优选是彼此相邻的。然而，该回路可以基于例如环长度要求，空间考虑因素和/或其他设计或功能因素由I / O引脚的非相邻连接形成。在另一个实施例中，第一和第二I / O引脚之间的连接通过使I / O引脚具有整体结构来建立。在另一个实施例中，第一和第二I / O引脚之间的连接通过位于封装衬底的表面上或该衬底内的金属化层来建立。通过在集成电路封装的范围内形成电感器环路，实现了对空间要求的实质性减少，这反过来又促进了小型化。而且，集成电路可以以各种系统中的任何一种来实现，其至少一个参数由封装的电感器环路的长度来控制。

9. 发明申请

WO2008036389A2 FREQUENCY SYNTHESIZER USING TWO PHASE LOCKED LOOPS 审中-公开
标题翻译：频率合成器采用两相锁定环
公开(公告)号：WO2008036389A2
公开(公告)日：2008-03-27
申请号：PCT/US2007020450
申请日：2007-09-21
申请人： GCT SEMICONDUCTOR INC , PARK JOONBAE , LEE KYEONGHO , KOO YIDO , LEE JEONG-WOO
发明人： PARK JOONBAE , LEE KYEONGHO , KOO YIDO , LEE JEONG-WOO
IPC分类号： H04B1/06
CPC分类号： H03L7/23 , H03L7/183 , H03L7/1976
摘要： The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and die second output frequency.
摘要翻译：该申请公开了涉及频率合成器的系统和方法实施例。频率合成器的实施例可以具有低相位噪声和窄信道间隔。频率合成器的实施例可以使用两个锁相环。频率合成器的一个实施例可以包括用于输出具有参考频率的信号的参考频率振荡器，基于参考频率信号生成第一输出频率信号的整数N锁相环，分频N锁相环基于参考频率信号和电路生成第二输出频率，以通过组合第一输出频率和第二输出频率来生成输出频率信号。

10. 发明申请

WO2005022598A3 INTEGRATED CIRCUIT PACKAGE HAVING INDUCTANCE LOOP FORMED FROM SAME-PIN-TO-SAME-BONDING-PAD STRUCTURE 审中-公开
标题翻译：集成电路封装具有形成于同一针一致结合垫结构的电感环
公开(公告)号：WO2005022598A3
公开(公告)日：2005-10-06
申请号：PCT/US2004027800
申请日：2004-08-27
申请人： GCT SEMICONDUCTOR INC , KOO YIDO , HUH HYUNGKI , LEE KANG YOON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
发明人： KOO YIDO , HUH HYUNGKI , LEE KANG YOON , LEE JEONG-WOO , PARK JOONBAE , LEE KYEONGHO
IPC分类号： H01L23/64 , H01L29/00
CPC分类号： H01L23/645 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/49111 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.
摘要翻译：集成电路封装包括由接合线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。在一个实施例中，电感回路由将集成电路芯片上的键合焊盘连接至封装的I / O引脚的第一导线和将相同键合焊盘连接至相同引脚的第二导线形成。通过在集成电路封装的范围内形成电感器环路，实现了对空间要求的实质性减少，这反过来又促进了小型化。

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