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1. 发明申请

WO1992013348A1 SEMICONDUCTOR STORING DEVICE 审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO1992013348A1
公开(公告)日：1992-08-06
申请号：PCT/JP1992000048
申请日：1992-01-22
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KATO, Yosiharu
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11C11/409
CPC分类号： G11C11/4076 , G11C7/1033 , G11C8/18
摘要： A semiconductor storing device is provided with a memory cell array (8) in connection with a data bus via a first selection circuit (6), a second selection circuit (7) responding to first control signals (Ζ0, Ζx), a third selection circuit (8) responding to second control signals (Ζ1 - Ζ8), a row address buffer (17) responding to the activation of a row address strobe signal, an address fetch circuit (21) which commands the fetch of a column address every predetermined number of toggled CAS signals, a column address buffer (19) responding to a third control signal fed from the address fetch circuit (21), a nibble decoder (38) for generating the first and second control signals, and a gate control circuit (39). During the period of activating row address strobe signal, after a column address is fetched, the next column address of the memory cell to be accessed is prefetched.
摘要翻译：半导体存储装置具有经由第一选择电路（6）连接到数据总线的存储器单元（8）的阵列，第二选择电路（7）响应于第一控制信号（phi0，pHix），第三选择电路（8），响应于第二控制信号（PHI1-PHI 8），一个行地址缓冲器（17），响应于发射的一个行选择脉冲信号，一个存储器地址读出电路（21），每次达到预定数量的信号时，该存储器地址读出电路（21）控制存储器中列地址的读出; “列选择脉冲引入，列地址缓冲器（19）响应于由所述存储器地址读出电路（21），一个半字节译码器提供的第三控制信号（38 ）用于产生第一和第二控制信号，以及控制电路（39）。在一个线选择脉冲信号的前序期间，一旦柱在存储器地址读出，存储单元的下一个列地址，其必须预先访问是读入内存。

2. 发明申请

WO1992005634A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：WO1992005634A1
公开(公告)日：1992-04-02
申请号：PCT/JP1991001244
申请日：1991-09-19
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KOMAKI, Masaki
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H03K17/16
CPC分类号： H03K19/01721
摘要： An output buffer circuit which comprises a group of inverters (11) mutually connected in multistage cascade, including at least an input stage inverter (11in) and an output stage inverter (11out). Further, an auxiliary circuit (13) is connected in parallel with the output buffer circuit. The auxiliary circuit (13) includes a first capacitor (C1) which charges an external capacitive load (Lc) in advance and a second capacitor (C2) which discharges the electric charge stored in the capacitive load (Lc) in advance.
摘要翻译：一种输出缓冲电路，包括以多级级联方式相互连接的一组反相器（11），至少包括输入级反相器（11in）和输出级反相器（11out）。此外，辅助电路（13）与输出缓冲电路并联连接。辅助电路（13）包括预先对外部电容性负载（Lc）充电的第一电容器（C1）和预先对容纳负载（Lc）中蓄积的电荷进行放电的第二电容器（C2）。

3. 发明申请

WO1992004770A1 DIFFERENTIAL AMPLIFYING CIRCUIT OF OPERATIONAL AMPLIFIER 审中-公开
标题翻译：操作放大器的差分放大电路
公开(公告)号：WO1992004770A1
公开(公告)日：1992-03-19
申请号：PCT/JP1991001212
申请日：1991-09-12
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , YAMASHITA, Masahiro , NISHIMURA, Hirokazu
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H03F03/45
CPC分类号： H03F3/45076 , H03F2203/45214
摘要： An operational amplifying circuit, the linearity of whose output voltage to the input voltage thereof can be ensured ranging from a first power supply to a second one. A differential circuit (1) comprising a first and a second FET transistor (T11, T12) having channels of a first conductive type, a current Miller circuit part (2) comprising a first and a second FET transistor (T13, T14) having channels of a second conductive type which are connected with the differential amplifying circuit (1) respectively, a constant current circuit part (3) which is connected to the differential amplifying circuit (1) on the second power supply (GND) side, and an output circuit part (4) comprising a third FET transistor (T7) of the second conductive type whose gate terminal is connected with the drain terminal of the second FET transistor (T12) and a constant current circuit. The potential (a) of the connecting part between the differential amplifying circuit part and the constant current circuit part (3) is set to zero volt or more when an input signal Vin is zero volt, and the potential difference between the potential (a) and the potential (b) of the gate of the third FET transistor is ensured in the whole range of the voltage change of the input signal Vin.

4. 发明申请

WO1992017000A1 CIRCUIT FOR CONVERTING LEVEL 审中-公开
标题翻译：转换电路
公开(公告)号：WO1992017000A1
公开(公告)日：1992-10-01
申请号：PCT/JP1992000325
申请日：1992-03-18
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , SEKI, Teruo , UKAI, Hiroaki
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H03K19/0175
CPC分类号： H03K19/017554 , H03K19/00369 , H03K19/017527
摘要： A circuit for converting a first logical level into a second one. Even when the voltage of a power supply is increased, the low level of the output voltage of a switching circuit (25) is suppressed from increasing, and accordingly an output buffer (28) is always made operable, because voltage limiting elements (26, 27) suppress the output level shift voltages of level-shifting devices (21, 22) connected to the output ends of input transistors (Q1, Q2) to predetermined values.

5. 发明申请

WO1992012535A1 PROCESS FOR FORMING SILICON OXIDE FILM 审中-公开
标题翻译：形成硅氧烷膜的工艺
公开(公告)号：WO1992012535A1
公开(公告)日：1992-07-23
申请号：PCT/JP1991001739
申请日：1991-12-19
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , TSUKUNE, Atsuhiro , FURUMURA, Yuji , HATANAKA, Masanobu
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H01L21/312
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02274 , H01L21/0228 , H01L21/0234 , H01L21/3121 , H01L21/3122 , H01L21/316 , H01L21/76819
摘要： A process for forming a silicon oxide film comprising the step of depositing a thin film of a silanol, a polymer thereof or a siloxane polymer, each containing an organic group, on a substrate by exciting a gas containing an organosilane or organosiloxane gas and a gas containing H and OH on a substrate in a reaction chamber to cause a reaction in a gas phase or on the substrate and the step of removing the organic group from the thin film by plasma treatment. Preferably the thin film is formed by repeating the depositing step and the removing step in the same chamber and is heat treated at a temperature of 450 °C or below. This process provides a good insulation film having a flatness comparable to that of an SOG film.

6. 发明申请

WO1992009084A1 SEMICONDUCTOR MEMORY HAVING HIGH-SPEED ADDRESS DECODER 审中-公开
标题翻译：具有高速地址解码器的半导体存储器
公开(公告)号：WO1992009084A1
公开(公告)日：1992-05-29
申请号：PCT/JP1991001563
申请日：1991-11-15
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KAWAMOTO, Satoru
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11C11/406
CPC分类号： G11C8/00 , G11C11/406 , G11C11/408
摘要： A semiconductor memory comprising a memory cell array (1), a first address bus (2) for transferring external address signals, a second address bus (3) for transferring internal address signals, an address decoder (4), and a controller (5); wherein the address decoder (4) includes a decoding section (4A) for decoding the address signal inputted to the address decoder (4) to select the predetermined word line of the memory cell array (1) and a changing section (4B) for changing the address signal to be inputted to the decoding section (4A) to the external or internal address signal by selecting either of the first and second address buses (2 and 3). Thus, it is possible to decrease the transfer time by transferring the external and internal address signals to the address decoder (4) through the first and second address buses (2 and 3) in accordance with an address activation signal before operation mode is decided and accelerate the access time of the memory cell by decreasing the decoding time.

7. 发明申请

WO1992003825A1 INITIALIZING CIRCUIT AND SEMICONDUCTOR DEVICE USING THEREOF 审中-公开
标题翻译：使用它的初始化电路和半导体器件
公开(公告)号：WO1992003825A1
公开(公告)日：1992-03-05
申请号：PCT/JP1991001143
申请日：1991-08-28
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KOUKETSU, Takashi , SEKI, Teruo
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11C11/34
CPC分类号： G11C7/1093 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C7/20 , G11C8/06
摘要： An initializing circuit (20) for setting the initial state of a latching circuit (30) in a semiconductor device when switching on a power supply. The initializing circuit is provided with a sensing circuit (TR1, TR2, R, 21) which operates according to switching on the power supply and senses that the power supply voltage (Vcc) increases to a predetermined voltage, and a circuit (22) for controlling output levels which responds to a sense signal (V1) outputted from the sensing circuit and pulls up the level of the output signal (Vout) of the initializing circuit to a high potential level or pulls down it to a low potential level. After the power is interrupted and when the power is supplied again, the latching circuit (30) is fed with the output signal controlled by the circuit (22) as its power source voltage. Consequently the latching circuit can be reliably initialized, and the malfunction on restart is prevented.

8. 发明申请

WO1992013344A1 ERROR CORRECTION PROCESSING DEVICE AND ERROR CORRECTION METHOD 审中-公开
标题翻译：错误校正处理设备和错误校正方法
公开(公告)号：WO1992013344A1
公开(公告)日：1992-08-06
申请号：PCT/JP1992000050
申请日：1992-01-22
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , NAKAGUCHI, Yukimi
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11B20/18
CPC分类号： G11B20/1833 , G06F11/10 , H03M13/151
摘要： An arithmetic operation processing method in an error correction processing device which is designed for high-speed chain search operation without increasing hardware quantity to reduce the time for correction processing. The error correction processing device has arithmetic circuits (141 to 159) that find solutions of the terms corresponding to the terms of an error position polynomial in which the elements read out from a recording medium are calculated from the data of code language consisting of Galois body, wherein the circuits (141 to 159) successively calculate values of terms for the variables consisting of Galois body of the polynomial in synchronism with the clock signals, the values of terms from the circuits (141 to 159) are added up through an EOR circuit (160) to find a solution of said error position polynomial, and presence or absence of error at the positions of the data is detected based on the solution, and wherein operations of said circuits (141 to 159) are carried out to successively find the solutions from the lower position through up to the upper position in said data that are read out.
摘要翻译：一种误差校正处理装置中的算术运算处理方法，其被设计用于高速链路搜索操作，而不增加硬件数量以减少校正处理的时间。误差校正处理装置具有运算电路（141〜159），其求出与由伽罗瓦体组成的代码语言的数据计算出的从记录介质读出的元素的误差位置多项式项对应的项的解，其中电路（141至159）与时钟信号同步地连续地计算由多项式的伽罗瓦体组成的变量的项的值，来自电路（141至159）的项的值通过EOR电路相加（160）以找到所述错误位置多项式的解，并且基于该解决方案检测在数据位置处的有无错误，并且其中执行所述电路（141至159）的操作以依次找到从读出的所述数据中的较低位置到上位置的解决方案。

9. 发明申请

WO1993001541A1 APPARATUS FOR SUM-OF-PRODUCT OPERATION 审中-公开
标题翻译：用于产品操作的装置
公开(公告)号：WO1993001541A1
公开(公告)日：1993-01-21
申请号：PCT/JP1992000819
申请日：1992-06-29
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , YAMADA, Kenji
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G06F07/52
CPC分类号： G06F9/3869 , G06F7/5443 , G06F2207/3884
摘要： An apparatus for sum-of-product operation includes a multiplier (1), a pipeline register (2) for holding the result of multiplication, and an adder (3) for adding the output of the pipeline register or an addend to an augend. Timing signal generation means (4) generates first and second timing signals (T1, T2) in synchronism with first and second clocks (CK1, CK2). A first instruction latch (5) holds an instruction in synchronism with the first timing signal (T1) and outputs a first control signal. A second instruction latch (6) holds the instruction held by the first instruction latch (5) in synchronism with the second timing signal (T2) and outputs a second control signal. A control signal selector (7) outputs the second control signal to the adder (3) in response to the first timing signal (T1), and outputs the first control signal to the adder (3) in response to the second timing signal (T2).

10. 发明申请

WO1992004774A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：WO1992004774A1
公开(公告)日：1992-03-19
申请号：PCT/JP1991001181
申请日：1991-09-04
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KURODA, Susumu , SEKI, Teruo
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H03K05/15
CPC分类号： H03K5/15 , G06F1/06 , G11C7/22 , G11C8/18 , H03K5/1504
摘要： A clock buffer which can output stably plural clock signals provided with predetermined time differences and generated from a reference clock signal. Plural informations stored in a predetermined storing means (4) are read out in synchronism with a predetermined clock pulse generated by a clock generating means (11). The read out information are transferred successively by synchronizing plural latch circuits (9, 10) of a latching means (30) with the predetermined clock pulse, and the information is outputted to another arithmetic processing circuit via a predetermined outputting means (31). The clock generating means (11) has a first pulse generating circuit (19) which outputs a first clock signal (CLK1) according to an inputted reference clock signal (CLK), and a second pulse generating circuit (20) which outputs a second clock signal (CLK2), responding to the first clock signal (CLK1).

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