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1. 发明申请

WO2010014289A1 BALUN SIGNAL TRANSFORMER AND METHOD OF FORMING 审中-公开
标题翻译：巴伦信号变换器及其形成方法
公开(公告)号：WO2010014289A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/043909
申请日：2009-05-14
申请人： FREESCALE SEMICONDUCTOR INC. , LIU, Lianjun , ABROKWAH, Jonathan, K. , HARTIN, Olin, L. , LI, Qiang
发明人： LIU, Lianjun , ABROKWAH, Jonathan, K. , HARTIN, Olin, L. , LI, Qiang
IPC分类号： H03H7/42
CPC分类号： H03H7/42 , H01F19/08 , H01F2017/0046 , H03H7/1758 , H03H7/1766 , H03H7/1775
摘要： A balanced-unbalanced (balun) signal transformer (48) includes an unbalanced port (30), a balanced port (50) coupled to the unbalanced port, the balanced port comprising a first terminal (52) and a second terminal (54), a first capacitor (90) coupled to the first terminal, a first inductor (92) coupled to ground and the first capacitor, a second capacitor (94) coupled to the second terminal, and a second inductor (96) coupled to ground and the second capacitor. The transformer may also include a third capacitor (84) coupled to a terminal of the unbalanced port; and a third inductor (82) coupled to the third capacitor and the third terminal.
摘要翻译：平衡不平衡（balun）信号变压器（48）包括不平衡端口（30），耦合到不平衡端口的平衡端口（50），平衡端口包括第一端子（52）和第二端子（54）耦合到第一端子的第一电容器（90），耦合到地的第一电感器（92）和第一电容器;耦合到第二端子的第二电容器（94）和耦合到地的第二电感器（96）和第二电容器。变压器还可以包括耦合到不平衡端口的端子的第三电容器（84）以及耦合到所述第三电容器和所述第三端子的第三电感器（82）。

2. 发明申请

WO2007130148A2 METHOD OF FABRICATING REDUCED SUBTHRESHOLD LEAKAGE CURRENT SUBMICRON NFET'S WITH HIGH III/V RATIO MATERIAL 审中-公开
标题翻译：制造具有高III / V比率材料的减少的底层漏电流基极NFET的方法
公开(公告)号：WO2007130148A2
公开(公告)日：2007-11-15
申请号：PCT/US2006/060819
申请日：2006-11-13
申请人： FREESCALE SEMICONDUCTOR INC. , GLASS, Elizabeth, C. , HARTIN, Olin, L. , HENRY, Haldane, S. , JAMET, Philippe, O. , ZHANG, Lisa, Z. , PELCZYNSKI, Michael, W.
发明人： GLASS, Elizabeth, C. , HARTIN, Olin, L. , HENRY, Haldane, S. , JAMET, Philippe, O. , ZHANG, Lisa, Z. , PELCZYNSKI, Michael, W.
IPC分类号： H01L29/739
CPC分类号： H01L29/7784
摘要： A method of fabricating an enhancement mode semiconductor device (50) comprises providing a compound semiconductor substrate (12), epitaxially growing on the substrate a first portion (14) of a buffer (11), the first portion (14) including gallium arsenide (GaAs), growing a second portion (15) of the buffer, the second portion (15) including a high V/III ratio and high aluminum (Al) mole fraction aluminum gallium arsenide (AlGaAs), and epitaxially growing a stack (10) of compound semiconductor layers on the buffer (11). An enhancement mode semiconductor device is then formed in the stack.
摘要翻译：一种制造增强型半导体器件（50）的方法包括提供化合物半导体衬底（12），在衬底上外延生长缓冲器（11）的第一部分（14），所述第一部分（14）包括砷化镓（ GaAs），生长缓冲器的第二部分（15），第二部分（15）包括高V / III比和高铝（Al）摩尔分数铝砷化镓（AlGaAs），并外延生长堆叠（10）的化合物半导体层在缓冲器（11）上。然后在堆叠中形成增强型半导体器件。

3. 发明申请

WO2006130260A2 INTEGRATED CIRCUIT WITH IMPROVED SIGNAL NOISE ISOLATION AND METHOD FOR IMPROVING SIGNAL NOISE ISOLATION 审中-公开
标题翻译：具有改进的信号噪声隔离的集成电路和用于改善信号噪声隔离的方法
公开(公告)号：WO2006130260A2
公开(公告)日：2006-12-07
申请号：PCT/US2006/015113
申请日：2006-04-21
申请人： FREESCALE SEMICONDUCTOR, INC. , BANERJEE, Suman, K. , FERRER, Enrique , HARTIN, Olin, L. , SECAREANU, Radu, M.
发明人： BANERJEE, Suman, K. , FERRER, Enrique , HARTIN, Olin, L. , SECAREANU, Radu, M.
CPC分类号： H01L27/0248 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground. The dedicated ground isolation pad (306) and the ground pad (304) collect noise that would normally propagate between the first and second noise sensitive circuits (120, 220) and additional circuits that share the same substrate (110).
摘要翻译：一种片上系统（SOC）（100）以及分离SOC中的噪声的方法，包括多个噪声敏感电路块（120,220）和ESD保护焊盘（302,304,306,308,310,312,312）和314）。 VDD隔离焊盘（302）连接到第一噪声敏感电路（120）的N阱环（124），以从基板（110）收集噪声，并将电路与P阱区域（112）隔离。接地保护焊盘（304）连接到第一噪声敏感电路（120）的隔离P阱（126）。接地焊盘（304）从隔离的P阱（126）收集噪声并将其发送到地面。专用接地隔离垫（306）连接到第二噪声敏感电路（220）的P阱环（224）。专用接地隔离垫（306）从P阱环（224）收集噪声并将其发送到地面。专用接地隔离焊盘（306）和接地焊盘（304）收集正常地在第一和第二噪声敏感电路（120,220）之间传播的噪声以及共享相同衬底（110）的附加电路。

4. 发明申请

WO2009094024A1 ELECTRONIC DEVICE WITH CONNECTION BUMPS 审中-公开
标题翻译：具有连接件的电子设备
公开(公告)号：WO2009094024A1
公开(公告)日：2009-07-30
申请号：PCT/US2008/051783
申请日：2008-01-23
申请人： FREESCALE SEMICONDUCTOR INC. , SECAREANU, Radu, M. , BANERJEE, Suman, K. , HARTIN, Olin, L. , WIPF, Sandra, J.
发明人： SECAREANU, Radu, M. , BANERJEE, Suman, K. , HARTIN, Olin, L. , WIPF, Sandra, J.
IPC分类号： H01L21/60 , H05K3/34
CPC分类号： H01L24/14 , H01L2224/14133 , H01L2224/17519 , H01L2924/01033 , H01L2924/14 , H01L2924/19043 , H01L2924/3011
摘要： Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (L m ). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.
摘要翻译：倒装芯片电子器件（40,70,80,90）使用用于耦合到外部衬底的凸块（42,72,82）。装置单元（43,73,83,93）和凸块（42,72,82）优选地布置成簇（46），其中四个凸块（42,72,82）基本上围绕每个器件单元（43,73,83） 93）或与十字交叉点处的设备单元（43,73,83,93）形成十字。凸起（42,72,82）期望地间隔开最小允许凸起（42,72,82）间距（Lm）。通常，取决于整个功能，每个设备单元（43,43,83,93）包含一个或多个有源器件区域（44,47,86,96）。复数器件（40,70）由簇（46）的XY阵列形成，其中相邻的簇（46）可共享凸块（43,43,83,93）和/或器件单元（43,43,83， 93）。在优选实施例中，凸块（42,82）形成装置（40,80,90）的外周边（48）。最大器件温度和总噪声降低。

5. 发明申请

WO2006025971A1 RECESSED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：接近半导体器件
公开(公告)号：WO2006025971A1
公开(公告)日：2006-03-09
申请号：PCT/US2005/026064
申请日：2005-07-22
申请人： FREESCALE SEMICONDUCTOR, INC. , LI, Hsin-Hua, P. , GREEN, Bruce, M. , HARTIN, Olin, L. , LAN, Ellen, Y. , WEITZEL, Charles, E.
发明人： LI, Hsin-Hua, P. , GREEN, Bruce, M. , HARTIN, Olin, L. , LAN, Ellen, Y. , WEITZEL, Charles, E.
IPC分类号： H01L31/0328
CPC分类号： H01L29/7785 , H01L21/28593 , H01L29/2003 , H01L29/66462
摘要： A semiconductor structure includes a first semiconductor layer (22), a second semiconductor layer (24) over the first semiconductor layer, a third semiconductor layer (25) over the second semiconductor layer, and a fourth semiconductor layer (26) over the third semiconductor layer. A first conductive portion (144) is coupled to the first semiconductor layer, and a second conductive portion (50) is formed over the first semiconductor layer.
摘要翻译：半导体结构包括第一半导体层（22），第一半导体层上的第二半导体层（24），第二半导体层上的第三半导体层（25）和第三半导体层上的第四半导体层（26）层。第一导电部分（144）耦合到第一半导体层，并且第二导电部分（50）形成在第一半导体层上。

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