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1. 发明申请

WO2006107419A2 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：WO2006107419A2
公开(公告)日：2006-10-12
申请号：PCT/US2006005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R
发明人： SADAKA MARIAM G , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件（10）的过程包括将应变Si（16）和压缩SiGe（28）与沟槽隔离（24）集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

2. 发明申请

WO2006039038A3 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 审中-公开
标题翻译：形成具有应变通道和异质结源极/漏极的半导体器件的方法
公开(公告)号：WO2006039038A3
公开(公告)日：2006-11-09
申请号：PCT/US2005031001
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR INC , THEAN VOON-YEW , SADAKA MARIAM G , WHITE TED R , BARR ALEXANDER L , KOLAGUNTA VENKAT R , NGUYEN BICH-YEN , VARTANIAN VICTOR H , ZHANG DA
发明人： THEAN VOON-YEW , SADAKA MARIAM G , WHITE TED R , BARR ALEXANDER L , KOLAGUNTA VENKAT R , NGUYEN BICH-YEN , VARTANIAN VICTOR H , ZHANG DA
IPC分类号： H01L21/44 , H01L21/3205 , H01L21/331 , H01L21/336 , H01L21/338 , H01L21/4763 , H01L21/8222
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：通过将栅极（22）置于优选为硅的半导体层（16）上来形成半导体器件（10）。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域上方。热过程将应力源材料扩散到半导体层中。发生横向扩散以形成应变材料层（30）紧邻应变通道的应变通道（17）的形成。扩展注入从应力源材料层的第一部分创建源极和漏极注入。应力源材料层的第二部分保留在应变沟道与源极和漏极注入物之间的沟道中。因此在应变通道中形成异质结。在另一种形式中，发生应激材料的氧化而不是延伸植入物以形成应变通道。

3. 发明申请

WO2005081748A3 SEMICONDUCTOR STRUCTURE HAVING STRAINED SEMICONDUCTOR AND METHOD THEREFOR 审中-公开
标题翻译：具有应变半导体的半导体结构及其方法
公开(公告)号：WO2005081748A3
公开(公告)日：2006-06-08
申请号：PCT/US2005001532
申请日：2005-01-12
申请人： FREESCALE SEMICONDUCTOR INC , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , SADAKA MARIAM G , THEAN VOON-YEW , WHITE TED R
发明人： BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , SADAKA MARIAM G , THEAN VOON-YEW , WHITE TED R
IPC分类号： H01L21/336 , H01L21/00 , H01L21/46 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823412 , H01L21/823807 , H01L21/84
摘要： A first semiconductor structure (10) has a silicon substrate (12), a first silicon germanium layer (14) grown on the silicon, a second silicon germanium layer (16) on the first silicon germanium layer (14), and a strained silicon layer (18) on the second silicon germanium layer (16). A second semiconductor structure (22) has a silicon substrate (24) and an insulating top layer (26). The silicon layer (18) of the first semiconductor structure (10) is bonded to the insulator layer (26) to form a third semiconductor structure (30). The second silicon germanium layer (16) is cut to separate most of the first semiconductor structure (10) from the third semiconductor structure (30). The silicon germanium layer (16) is removed to expose the strained silicon layer (18) where transistors (32 & 34) are subsequently formed, which is then the only layer remaining from the first semiconductor structure (10). The transistors (32 & 34) are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer (24) of the second semiconductor structure.
摘要翻译：第一半导体结构（10）具有硅衬底（12），在硅上生长的第一硅锗层（14），第一硅锗层（14）上的第二硅锗层（16）和应变硅层（18）在第二硅锗层（16）上。第二半导体结构（22）具有硅衬底（24）和绝缘顶层（26）。第一半导体结构（10）的硅层（18）接合到绝缘体层（26）以形成第三半导体结构（30）。切割第二硅锗层（16）以将大部分第一半导体结构（10）与第三半导体结构（30）分离。去除硅锗层（16）以暴露应变硅层（18），其中随后形成晶体管（32和34），其然后是从第一半导体结构（10）剩余的唯一层。晶体管（32和34）沿第一半导体结构的基极硅层（24）的<100>方向和<100>方向成45度角。

4. 发明申请

WO2007092655A3 METHOD TO SELECTIVELY FORM REGIONS HAVING DIFFERING PROPERTIES AND STRUCTURE 审中-公开
标题翻译：选择性区域具有不同性质和结构的方法
公开(公告)号：WO2007092655A3
公开(公告)日：2007-12-21
申请号：PCT/US2007060259
申请日：2007-01-09
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , NGUYEN BICH-YEN , THEAN VOON-YEW , WHITE TED R
发明人： SADAKA MARIAM G , NGUYEN BICH-YEN , THEAN VOON-YEW , WHITE TED R
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , Y10S438/973
摘要： A semiconductor device is formed having two physically separate regions (16, 28) with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer (16) having a first property is formed on an insulating layer (14). The first layer is isolated into first (16) and second (28) physically separate areas. After this physical separation, only the first area (28) is amorphized. A donor wafer (30) is placed in contact with the first (28) and second (16) areas. The semiconductor device (10) is annealed to modify the first (28) of the first (28) and second (16) separate areas to have a different property from the second of the first and second separate areas. The donor wafer (30) is removed and at least one semiconductor structure (32, 34) is formed in each of the first (28) and second (16) physically separate areas. In another form, the separate regions (114) are a bulk substrate (112) and an electrically isolated region (116) within the bulk substrate (112).
摘要翻译：形成具有两个物理上分离的区域（16,28）的半导体器件，所述区域具有不同的性质，例如不同的表面取向，晶体旋转，应变或组成。在一种形式中，在绝缘层（14）上形成具有第一特性的第一层（16）。第一层被隔离成第一（16）和第二（28）物理上分开的区域。在物理分离之后，只有第一区域（28）被非晶化。施主晶片（30）放置成与第一（28）和第二（16）区域接触。对半导体器件（10）进行退火以修改第一（28）和第二（16）分离区域的第一（28）以具有与第一和第二分离区域中的第二个不同的特性。施主晶片（30）被移除并且在第一（28）和第二（16）物理分离区域中的每一个中形成至少一个半导体结构（32,34）。在另一种形式中，分离区域（114）是体衬底（112）内的体衬底（112）和电隔离区域（116）。

5. 发明申请

WO2005034191A3 TEMPLATE LAYER FORMATION 审中-公开
标题翻译：模板层形成
公开(公告)号：WO2005034191A3
公开(公告)日：2006-03-09
申请号：PCT/US2004030088
申请日：2004-09-14
申请人： FREESCALE SEMICONDUCTOR INC , LIU CHUN-LI , SADAKA MARIAM G , BARR ALEXANDER L , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R , XIE QIANGHUA
发明人： LIU CHUN-LI , SADAKA MARIAM G , BARR ALEXANDER L , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R , XIE QIANGHUA
IPC分类号： H01L20060101 , H01L21/00 , H01L21/31 , H01L21/331 , H01L21/336 , H01L21/338 , H01L21/8234 , H01L21/84
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

6. 发明申请

WO2007114983A2 METHOD OF MAKING A MULTIPLE CRYSTAL ORIENTATION SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造多晶体取向半导体器件的方法
公开(公告)号：WO2007114983A2
公开(公告)日：2007-10-11
申请号：PCT/US2007062793
申请日：2007-02-26
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , NGUYEN BICH-YEN , WHITE TED R
发明人： SADAKA MARIAM G , NGUYEN BICH-YEN , WHITE TED R
IPC分类号： H01L23/48
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
摘要翻译：以增强的性能晶体取向形成的晶体管的方法从具有第一表面取向的半导体衬底（12,52），半导体衬底上的薄蚀刻停止层（14,54），掩埋氧化物层（ 16,56）和在所述掩埋氧化物层上的第二表面取向的半导体层（18,58）。蚀刻渗透到薄的蚀刻停止层。被选择以最小化对下面的半导体衬底的损害的另一蚀刻暴露了半导体衬底的一部分。然后从半导体衬底的暴露部分生长外延半导体（28,66）以形成具有第一表面取向并且具有很少（如果有的话）缺陷的半导体区域。然后外延生长的半导体区域用于增强一种晶体管，而第二表面取向的半导体层用于增强不同类型的晶体管。

7. 发明申请

WO2005112094A3 METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM 审中-公开
标题翻译：使用硅锗制备半导体结构的方法
公开(公告)号：WO2005112094A3
公开(公告)日：2007-06-28
申请号：PCT/US2005011552
申请日：2005-04-05
申请人： FREESCALE SEMICONDUCTOR INC , ORLOWSKI MARIUS K , BARR ALEXANDER L , SADAKA MARIAM G , WHITE TED R
发明人： ORLOWSKI MARIUS K , BARR ALEXANDER L , SADAKA MARIAM G , WHITE TED R
IPC分类号： H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer (24,26,28) is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate (12,14,24,26,28) having an oxide layer (14) underlying the silicon layer (24,26,28). An amorphous or polycrystalline silicon germanium layer (32) is formed overlying the silicon layer (24,26,28). Alternatively, germanium is implanted into a top portion of the silicon layer (24,26,28) to form an amorphous silicon germanium layer (32). The silicon germanium layer (32) is then oxidized to convert the silicon germanium layer into a silicon dioxide layer (34) and to convert at least a portion of the silicon layer (24,26,28) into germanium-rich silicon (36,38). The silicon dioxide layer (34) is then removed prior to forming transistors (48,50,52) using the germanium-rich silicon (36,38). In one embodiment, the germanium-rich silicon (36,38) is selectively formed using a patterned masking layer (30) over the silicon layer (28) and under the silicon germanium layer (32). Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供具有硅层（24,26,28）的半导体衬底。在一个实施例中，衬底是在硅层（24,26,28）下方具有氧化物层（14）的绝缘体上硅（SOI）衬底（12,14,24,26,28）。在硅层（24,26,28）上形成非晶或多晶硅锗层（32）。或者，将锗注入硅层（24,26,28）的顶部以形成非晶硅锗层（32）。硅锗层（32）然后被氧化以将硅锗层转化成二氧化硅层（34）并将至少一部分硅层（24,26,28）转化为富含锗的硅（36， 38）。然后在使用富锗的硅（36,38）形成晶体管（48,50,52）之前去除二氧化硅层（34）。在一个实施例中，富锗富硅（36,38）使用硅层（28）上方的图案化掩模层（30）和硅锗层（32）下选择性地形成。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

8. 发明申请

WO2005112094A2 METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM 审中-公开
标题翻译：使用硅锗制备半导体结构的方法
公开(公告)号：WO2005112094A2
公开(公告)日：2005-11-24
申请号：PCT/US2005011552
申请日：2005-04-05
申请人： FREESCALE SEMICONDUCTOR INC , ORLOWSKI MARIUS K , BARR ALEXANDER L , SADAKA MARIAM G , WHITE TED R
发明人： ORLOWSKI MARIUS K , BARR ALEXANDER L , SADAKA MARIAM G , WHITE TED R
IPC分类号： H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer (24,26,28) is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate (12,14,24,26,28) having an oxide layer (14) underlying the silicon layer (24,26,28). An amorphous or polycrystalline silicon germanium layer (32) is formed overlying the silicon layer (24,26,28). Alternatively, germanium is implanted into a top portion of the silicon layer (24,26,28) to form an amorphous silicon germanium layer (32). The silicon germanium layer (32) is then oxidized to convert the silicon germanium layer into a silicon dioxide layer (34) and to convert at least a portion of the silicon layer (24,26,28) into germanium-rich silicon (36,38). The silicon dioxide layer (34) is then removed prior to forming transistors (48,50,52) using the germanium-rich silicon (36,38). In one embodiment, the germanium-rich silicon (36,38) is selectively formed using a patterned masking layer (30) over the silicon layer (28) and under the silicon germanium layer (32). Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供具有硅层（24,26,28）的半导体衬底。在一个实施例中，衬底是在硅层（24,26,28）下方具有氧化物层（14）的绝缘体上硅（SOI）衬底（12,14,24,26,28）。在硅层（24,26,28）上形成非晶或多晶硅锗层（32）。或者，将锗注入硅层（24,26,28）的顶部以形成非晶硅锗层（32）。硅锗层（32）然后被氧化以将硅锗层转化成二氧化硅层（34）并将至少一部分硅层（24,26,28）转化为富含锗的硅（36， 38）。然后在使用富锗的硅（36,38）形成晶体管（48,50,52）之前去除二氧化硅层（34）。在一个实施例中，富锗富硅（36,38）使用硅层（28）上方的图案化掩模层（30）和硅锗层（32）下选择性地形成。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

9. 发明申请

WO2007130151A3 SOI ACTIVE LAYER WITH DIFFERENT SURFACE ORIENTATION 审中-公开
标题翻译：具有不同表面方位的SOI主动层
公开(公告)号：WO2007130151A3
公开(公告)日：2008-03-27
申请号：PCT/US2006061274
申请日：2006-11-28
申请人： FREESCALE SEMICONDUCTOR INC , ADETUTU OLUBUNMI O , JONES ROBERT E , WHITE TED R
发明人： ADETUTU OLUBUNMI O , JONES ROBERT E , WHITE TED R
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures (201, 203, 205) having a first surface orientation are formed on a donor wafer (101). Semiconductor structures (401, 403, 405) having a second surface orientation are formed on a second wafer (301). Receptor openings are formed on the second wafer (301). The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
摘要翻译：具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。在一个示例中，在施主晶片（101）上形成具有第一表面取向的半导体结构（201,203,205）。具有第二表面取向的半导体结构（401,403,405）形成在第二晶片（301）上。受体开口形成在第二晶片（301）上。具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

10. 发明申请

WO2008014031A2 TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY 审中-公开
标题翻译：不对称数据存储电路的晶体管
公开(公告)号：WO2008014031A2
公开(公告)日：2008-01-31
申请号：PCT/US2007068086
申请日：2007-05-03
申请人： FREESCALE SEMICONDUCTOR INC , WHITE TED R , BURNETT JAMES D , WINSTEAD BRIAN A
发明人： WHITE TED R , BURNETT JAMES D , WINSTEAD BRIAN A
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823814 , H01L27/0922
摘要： A transistor (22) having a source (30) with higher resistance than its drain (40) is optimal as a pull-up device (20) in a storage circuit (10). The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region (50) is adjacent the source region for controlling electrical conduction of the transistor. A drain region (40) is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.
摘要翻译：具有比漏极（40）更高的电阻的源极（30）的晶体管（22）作为存储电路（10）中的上拉装置（20）是最佳的。晶体管具有源极区域，源极源极具有源极电阻。来源地区没有水淹。控制电极区域（50）与源极区域相邻，用于控制晶体管的导电。漏极区域（40）与控制电极区域相邻并与源极区域相对。漏极区域具有被浸没并具有漏极电阻的漏极注入。源极电阻大于漏极电阻，因为源极区域具有不同于漏极区域的物理性质。

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