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1. 发明申请

WO2013066798A1 MULTI-CORE INTERCONNECT IN A NETWORK PROCESSOR 审中-公开
标题翻译：网络处理器中的多核连接
公开(公告)号：WO2013066798A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/062378
申请日：2012-10-29
申请人： CAVIUM, INC.
发明人： KESSLER, Richard, E. , ASHER, David, H. , PERVEILER, John, M. , DOBBIE, Bradley, D.
IPC分类号： G06F12/08 , G06F15/78
CPC分类号： G06F12/0813 , G06F12/08
摘要： A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.
摘要翻译：网络处理器包括用于处理分组数据的多个处理器核。为了向处理器核提供对存储器子系统的访问，互连电路指导处理器核与L2 Cache和其他存储器件之间的通信。处理器核心分为几组，每组共享一条单独的总线，二级缓存分为多个银行，每个银行都可以访问单独的总线。互连电路处理在多个总线上存储和检索来自处理器核心的数据的请求，并处理从缓存存储器返回数据的响应。因此，网络处理器为多个处理器内核提供高带宽存储器访问。

2. 发明申请

WO2015138312A1 METHOD AND APPARATUS FOR TRANSFER OF WIDE COMMAND AND DATA BETWEEN A PROCESSOR AND COPROCESSOR 审中-公开
标题翻译：处理器与协处理器之间传送宽指令和数据的方法和装置
公开(公告)号：WO2015138312A1
公开(公告)日：2015-09-17
申请号：PCT/US2015/019426
申请日：2015-03-09
申请人： CAVIUM, INC.
发明人： SNYDER, Wilson, P. , KESSLER, Richard, E. , BERTONE, Michael, S.
IPC分类号： G06F15/76 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3881 , G06F15/17337 , G06F15/76
摘要： According to at least one example embodiment, a method of processing a wide command includes storing wide command data in a first physical structure of a processor. Information associated with the wide command is determined based on the wide command data and/or a corresponding memory address range associated with the wide command. The information associated with the wide command determined includes a size of the wide command and is stored in a second physical structure of the processor. The processor causes the wide command data and the information associated with the wide command to be provided directly to a coprocessor for executing the wide command. The processor and the coprocessor may reside on a single chip device. Alternatively, the processor and the coprocessor may reside on separate chip devices in a multi-chip system.
摘要翻译：根据至少一个示例性实施例，处理宽命令的方法包括将宽命令数据存储在处理器的第一物理结构中。与宽命令相关联的信息基于宽命令数据和/或与宽命令相关联的相应存储器地址范围来确定。与所确定的广泛命令相关联的信息包括宽命令的大小并存储在处理器的第二物理结构中。处理器使宽命令数据和与宽命令相关联的信息直接提供给协处理器以执行宽命令。处理器和协处理器可以驻留在单个芯片设备上。或者，处理器和协处理器可以驻留在多芯片系统中的单独的芯片装置上。

3. 发明申请

WO2015134098A1 INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM 审中-公开
标题翻译：用于多芯片系统的互连互连协议
公开(公告)号：WO2015134098A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/072799
申请日：2014-12-30
申请人： CAVIUM, INC.
发明人： AKKAWI, Isam , KESSLER, Richard, E. , ASHER, David, H. , CHIN, Bryan, W. , SNYDER, Wilson, P.
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F3/0683 , G06F12/0813 , G06F12/0822 , G06F12/0828 , G06F12/0831 , G06F12/084 , G06F13/1663 , G06F2212/154 , G06F2212/62 , G06F2212/621
摘要： A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.
摘要翻译：多芯片系统包括配置为彼此通信并共享资源的多个芯片装置。根据至少一个示例性实施例，在多芯片系统内提供存储器一致性的方法包括在多芯片系统的第一芯片装置处保持指示一个或多个副本的一个或多个状态的状态信息，驻留在在多芯片系统的一个或多个芯片装置中的数据块。数据块存储在与多个芯片器件中的一个相关联的存储器中。第一芯片装置从多个芯片装置的第二芯片装置接收与数据块的一个或多个副本的副本相关联的消息，并且作为响应，执行基于状态确定的一个或多个动作的方案在第一芯片设备上维护的信息和接收到的消息。

4. 发明申请

WO2013062708A1 SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS 审中-公开
标题翻译：使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法
公开(公告)号：WO2013062708A1
公开(公告)日：2013-05-02
申请号：PCT/US2012/057269
申请日：2012-09-26
申请人： CAVIUM, INC.
发明人： PANGBORN, Jeffrey , BOUCHARD, Gregg, A. , GOYAL, Rajan , KESSLER, Richard, E.
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/1018 , G06F12/0292 , G06F12/06 , G06F2212/174 , G06F2212/2532
摘要： In one embodiment, a system comprises a plurality of memory ports (608A-608D). The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index and each of the memory ports have an individual wait time based on a respective workload. The system further comprises a first address hashing unit (602B) configured to receive a read request including a virtual memory address. The virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data.. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller (604) configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.
摘要翻译：在一个实施例中，系统包括多个存储器端口（608A-608D）。存储器端口被分配到多个子集中，其中每个子集由子集索引标识，并且每个存储器端口基于各自的工作负载具有单独的等待时间。该系统还包括：第一地址散列单元（602B），被配置为接收包括虚拟存储器地址的读取请求。虚拟内存地址与复制因子相关联，虚拟内存地址是指图形数据。第一地址哈希单元将复制因子转换为基于虚拟内存地址的相应子集索引，并将虚拟内存地址转换为一个基于硬件的内存地址。基于硬件的地址是指由相应子集索引指示的子集内的存储器端口中的图形数据。该系统还包括存储器复制控制器（604），其被配置为将读取请求引导到基于硬件的地址，由具有最低个人等待时间的相应子集索引所指示的子集内的存储器端口之一引导。

5. 发明申请

WO2013058925A1 PROCESSOR WITH EFFICIENT WORK QUEUING 审中-公开
标题翻译：加工者有效的工作队伍
公开(公告)号：WO2013058925A1
公开(公告)日：2013-04-25
申请号：PCT/US2012/056059
申请日：2012-09-19
申请人： CAVIUM, INC.
发明人： KESSLER, Richard, E. , MAHESHWARI, Aseem , SANZONE, Robert
IPC分类号： G06F9/50 , G06F9/48
CPC分类号： G06F9/5027 , G06F9/4881 , G06F2209/509
摘要： Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory linked-lists to the network services processor in response to availability of processing resources in the network services processor.
摘要翻译：提交给协处理器的工作通过多个输入队列之一进入，用于提供各种服务质量水平。存储器内链接列表存储由网络服务处理器执行的工作，以响应网络服务处理器中的处理资源的缺乏。响应于网络服务处理器中的处理资源的可用性，将工作从内存中链接列表移回到网络服务处理器。

6. 发明申请

WO2015134103A1 METHOD AND SYSTEM FOR ORDERING I/O ACCESS IN A MULTI-NODE ENVIRONMENT 审中-公开
标题翻译：用于在多节点环境中订购I / O访问的方法和系统
公开(公告)号：WO2015134103A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/072816
申请日：2014-12-30
申请人： CAVIUM, INC.
发明人： KESSLER, Richard, E.
IPC分类号： G06F13/20 , G06F5/06
CPC分类号： G06F13/423 , G06F12/0822 , G06F12/0833 , G06F13/10 , G06F13/20
摘要： According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of synchronizing access to an input/output (I/O) device in the multi-chip system comprises initiating, by a first agent of the multi-chip system, a first operation for accessing the I/O device, the first operation is queued, prior to execution by the I/O device, in a queue. Once the first operation is queued, an indication of such queuing is provided. Upon detecting, by a second agent of the multi-chip system, the indication of queuing the first operation in the queue, initiating a second operation to access the I/O device, the second operation is queued subsequent to the first operation in the queue.
摘要翻译：根据至少一个示例性实施例，多芯片系统包括被配置为彼此通信并共享诸如I / O设备之类的资源的多个芯片设备。根据至少一个示例性实施例，一种使对多芯片系统中的输入/输出（I / O）设备的访问同步的方法包括由多芯片系统的第一代理启动用于访问 I / O设备，第一个操作在I / O设备执行之前排队等待队列。一旦第一操作排队，就提供这种排队的指示。在由多芯片系统的第二代理检测到排队队列中的第一操作的指示时，启动访问I / O设备的第二操作，第二操作在队列中的第一操作之后排队。

7. 发明申请

WO2015134101A1 METHOD AND SYSTEM FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM 审中-公开
标题翻译：多芯片系统中的工作调度方法与系统
公开(公告)号：WO2015134101A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/072811
申请日：2014-12-30
申请人： CAVIUM, INC.
发明人： KESSLER, Richard, E. , SNYDER, Wilson, P., II
IPC分类号： G06F9/50
CPC分类号： G06F9/4881 , G06F3/0604 , G06F3/0631 , G06F3/0656 , G06F3/0673 , G06F9/5016 , G06F9/5072 , G06F12/023 , G06F2209/486 , G06F2212/1044
摘要： According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.
摘要翻译：根据至少一个示例性实施例，多芯片系统包括被配置为彼此通信并共享硬件资源的多个芯片装置。根据至少一个示例性实施例，一种在多芯片系统中处理工作项的方法包括：通过与芯片装置相关联的工作源组件（被称为源芯片装置）指定多个芯片装置，工作项目到调度程序进行调度。调度器然后将工作项目分配给用于处理的多个芯片装置的称为目标芯片装置的另一芯片装置，调度器是每个与多个芯片装置的相应芯片装置相关联的一个或多个调度器之一。

8. 发明申请

WO2015130404A1 PACKET SHAPING IN A NETWORK PROCESSOR 审中-公开
标题翻译：网络处理器中的分组形式
公开(公告)号：WO2015130404A1
公开(公告)日：2015-09-03
申请号：PCT/US2014/072835
申请日：2014-12-30
申请人： CAVIUM, INC.
发明人： FOLSOM, Brian, Robert , TOMPKINS, Joseph, B. , SNYDER, Wilson, P., II , KESSLER, Richard, E. , LANGEVIN, Edwin , JONES, Andrew, J. , ROBBINS, Ethan, F.
IPC分类号： G06F13/42 , H04L12/861
CPC分类号： H04L47/821 , G06F13/42 , H04L45/566 , H04L45/74 , H04L49/90 , H04L69/22
摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.
摘要翻译：电路用于管理网络分组处理器中的分组的传送。该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE与分组相关联的分组传输速率与峰值速率和与分组相关联的承诺速率中的至少一个进行比较，并且基于比较确定在多个分组之间传送分组的顺序。一旦分组被安排传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。然后，PEB使处理的分组被发送到目的地。

9. 发明申请

WO2015130403A1 PACKET SCHEDULING IN A NETWORK PROCESSOR 审中-公开
标题翻译：网络处理器中的分组调度
公开(公告)号：WO2015130403A1
公开(公告)日：2015-09-03
申请号：PCT/US2014/072826
申请日：2014-12-30
申请人： CAVIUM, INC.
发明人： FOLSOM, Brian, Robert , TOMPKINS, Joseph, B. , SNYDER, Wilson, P., II , KESSLER, Richard, E. , LANGEVIN, Edwin , JONES, Andrew, J. , ROBBINS, Ethan, Frederick
IPC分类号： H04L12/947 , H04L12/721
CPC分类号： H04L45/74 , H04L45/36 , H04L45/566 , H04L47/821 , H04L49/25 , H04L69/22
摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.
摘要翻译：电路用于管理网络分组处理器中的分组的传送。该电路包括分组描述符管理器（PDM），分组调度引擎（PSE）以及分组引擎和缓冲模块（PEB）。 PDM从命令信号生成元包和描述符，其中命令信号标识要由电路发送的分组。 PSE通过网络拓扑的模型对分组进行建模，根据建模确定在多个分组之间传输分组的顺序。一旦分组被调度以进行传输，PEB就根据描述符中指示的指令对分组执行处理操作以产生处理的分组。然后，PEB使处理的分组被发送到目的地。

10. 发明申请

WO2015134100A1 METHOD AND APPARATUS FOR MEMORY ALLOCATION IN A MULTI-NODE SYSTEM 审中-公开
标题翻译：多节点系统中记忆分配的方法与装置
公开(公告)号：WO2015134100A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/072808
申请日：2014-12-30
申请人： CAVIUM, INC.
发明人： KESSLER, Richard, E. , SNYDER, Wilson, P.
IPC分类号： G06F13/16
CPC分类号： G06F3/0608 , G06F3/0631 , G06F3/0659 , G06F3/0673 , G06F13/1657
摘要： According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet.
摘要翻译：根据至少一个示例性实施例，多芯片系统包括被配置为彼此通信并共享资源的多个芯片装置。根据至少一个示例实施例，多芯片系统中的存储器分配的方法包括通过多芯片系统中的一个或多个空闲池分配器（FPA）协处理器中的每一个来管理相应的免费池池列表缓存指针基于由一个或多个FPA协处理器管理的一个或多个空闲缓冲器指针列表，存储器分配器（MA）硬件组件将与多个芯片设备的芯片设备相关联的空闲缓冲区分配给与工作项目。根据至少一个方面，与工作项相关联的数据表示数据分组。

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