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1. 发明申请

WO9903241A2 DEMODULATING APPARATUS FOR OBTAINING DIGITAL INFORMATION 审中-公开
标题翻译：用于获取数字信息的解调装置
公开(公告)号：WO9903241A2
公开(公告)日：1999-01-21
申请号：PCT/GB9802022
申请日：1998-07-10
申请人： CAMBRIDGE CONSULTANTS , YOUNG ROBERT WILLIAM , COLLIER JAMES DIGBY YARLET
发明人： YOUNG ROBERT WILLIAM , COLLIER JAMES DIGBY YARLET
IPC分类号： H04L25/06 , H04L27/00
CPC分类号： H04L25/063
摘要： Demodulating apparatus for obtaining digital information from a modulated carrier signal, the digital information comprising a sequence of digital symbols, each digital symbol being defined by the modulation of the carrier signal over a symbol time period. The apparatus comprises a threshold generating device (8) which generates an analogue threshold signal; and a comparator device (3) having a signal input (4) which receives the modulated carrier signal, a threshold input (5, 6) which receives the threshold signal, and an output (7). The comparator device (3) compares the modulated carrier signal with the threshold signal and generates a digital signal in accordance with the result of the comparison, each digital signal representing a respective digital symbol, and wherein the threshold signal generated by the threshold generating device is determined in accordance with the N previously generated digital signals.
摘要翻译：一种用于从调制载波信号获得数字信息的解调装置，该数字信息包括数字符号序列，每个数字符号由符号时间段上的载波信号的调制定义。该装置包括产生模拟阈值信号的阈值产生装置（8）以及具有接收所述调制载波信号的信号输入端（4），接收所述阈值信号的阈值输入端（5,6）和输出端（7）的比较器装置（3）。比较器装置（3）将经调制的载波信号与阈值信号进行比较，并根据比较结果生成数字信号，每个数字信号表示相应的数字符号，其中由阈值产生装置产生的阈值信号为根据N个先前生成的数字信号确定。

2. 发明申请

WO9609583A2 DATA PROCESSING CIRCUITS AND INTERFACES 审中-公开
标题翻译：数据处理电路和接口
公开(公告)号：WO9609583A2
公开(公告)日：1996-03-28
申请号：PCT/GB9502283
申请日：1995-09-25
申请人： CAMBRIDGE CONSULTANTS , BARLOW STEPHEN JOHN , MORFEY ALISTAIR GUY , COLLIER JAMES DIGBY YARLET
发明人： BARLOW STEPHEN JOHN , MORFEY ALISTAIR GUY , COLLIER JAMES DIGBY YARLET
IPC分类号： G06F7/57 , G06F9/30 , G06F9/302 , G06F9/38 , G06F11/267 , G06F11/36
CPC分类号： G06F7/57 , G06F1/3203 , G06F1/3237 , G06F9/30 , G06F9/30014 , G06F9/30032 , G06F9/3005 , G06F9/30083 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/322 , G06F9/324 , G06F9/3869 , G06F11/2236 , G06F11/3648 , G06F11/3656 , G06F15/7832 , Y02D10/128 , Y02D50/20
摘要： An integrated circuit contains (102) a microprocessor core (100), program memory (104) and separate data storage (106, 108), together with analogue and digital signal processing circuitry (110). The ALU (302) is 16 bits wide, but a 32-bit shift unit (312) is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SER IN, SER OUT, SER-CLK, SER LOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space (104-110) of the processor core (100), without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimise power consumption.
摘要翻译：集成电路与模拟和数字信号处理电路（110）一起包含（102）微处理器核心（100），程序存储器（104）和单独的数据存储器（106,108）。 ALU（302）是16位宽，但是使用一对16位寄存器来提供32位移位单元（312）。处理器具有固定长度的指令格式，其中指令集包括在多个周期内使用移位单元的乘法和除法运算。不提供中断。集成电路的外部引脚允许单步和其他调试操作，以及允许外部通信测试数据或工作数据的串行接口（SIF）。串行接口具有四条线（SER IN，SER OUT，SER-CLK，SER LOADB），允许与主设备进行握手，以及允许直接访问处理器核心（100）的存储空间（104-110），而无需特定的程序控制。在每个处理器周期内，处理器电路被分成多个级，并且锁存器插在两个级之间以使功耗最小化。

3. 发明申请

WO2007034133B1 ANTENNA DIVERSITY 审中-公开
标题翻译：天线多样性
公开(公告)号：WO2007034133B1
公开(公告)日：2007-05-18
申请号：PCT/GB2006003272
申请日：2006-09-04
申请人： CAMBRIDGE SILICON RADIO LTD , COLLIER JAMES DIGBY YARLET , SINGER STEVE
发明人： COLLIER JAMES DIGBY YARLET , SINGER STEVE
IPC分类号： H04B7/08 , H04B1/713
CPC分类号： H04B7/0805 , H04B1/713
摘要： A communication device for receiving a signal in the form of a series of bursts, each burst being at one of a plurality of different available transmission modes, the communication device comprising: two antennas; a receiver unit coupled to the antennas for preferentially receiving signals from a selected one of the antennas; and an antenna selection unit for selecting for each received burst with which of the antennas the receiver unit is to preferentially receive signals.
摘要翻译：一种通信设备，用于以一系列突发的形式接收信号，每个突发处于多个不同的可用传输模式中的一个，所述通信设备包括：两个天线; 耦合到天线的接收机单元，用于优先接收来自所选天线之一的信号; 以及天线选择单元，用于为每个接收到的脉冲串选择接收器单元优先接收哪些天线的信号。

4. 发明申请

WO2009095280A2 INTEGRATED SIGNAL RECEIVER 审中-公开
标题翻译：集成信号接收器
公开(公告)号：WO2009095280A2
公开(公告)日：2009-08-06
申请号：PCT/EP2009050007
申请日：2009-01-02
申请人： CAMBRIDGE SILICON RADIO LTD , COLLIER JAMES DIGBY YARLET
发明人： COLLIER JAMES DIGBY YARLET
IPC分类号： H04B1/38 , G01S1/00 , H04B1/40
CPC分类号： H04B1/3805 , G01S19/35 , H04B1/406
摘要： A signal receiver having: an input for receiving radio signals; a clock; a receiving section for processing signals received at the input, the receiving section being configured to operate in: (a) a first mode for processing the received signals in accordance with a first protocol and in dependence on the state of the clock, and (b) a second mode for processing the received signal in accordance with a second protocol by steps including storing a sample of data received in accordance with the second protocol together with a representation of the state of the clock when that data was received, and subsequently comparing a timing indicated by the content of the stored sample of data with the timing indicated by the stored state of the clock.
摘要翻译：一种信号接收器，具有：用于接收无线电信号的输入; 一个钟; 接收部分，用于处理在所述输入端处接收的信号，所述接收部分被配置为以：（a）用于根据第一协议并依据所述时钟的状态处理所述接收信号的第一模式，以及（b ）第二模式，用于根据第二协议通过以下步骤来处理接收到的信号：包括存储根据第二协议接收的数据的样本以及当接收到该数据时的时钟的状态的表示，并且随后比较由存储的数据样本的内容指示的时间与由时钟的存储状态指示的时间。

5. 发明申请

WO02063462A3 GENERATING RANDOM DATA 审中-公开
标题翻译：生成随机数据
公开(公告)号：WO02063462A3
公开(公告)日：2002-10-03
申请号：PCT/GB0200300
申请日：2002-01-28
申请人： CAMBRIDGE SILICON RADIO LTD , COLLIER JAMES DIGBY YARLET
发明人： COLLIER JAMES DIGBY YARLET
IPC分类号： G06F7/58 , G09C1/00
CPC分类号： G06F7/588 , G06F7/582
摘要： A method for generating random data, the method comprising repeatedly performing a series of operations, and the series of operations comprising processing a seed value to generate a resulting value for use as the seed value in a subsequent performance of the series of operations and to generate output random data; wherein the series of operations also comprises: determining whether a predetermined amount of new truly random data is available; and if such data is available, modifying the generation of at least the resulting value in dependence on the new truly random data.
摘要翻译：一种用于产生随机数据的方法，所述方法包括重复执行一系列操作，并且所述一系列操作包括处理种子值以生成结果值，以用作所述一系列操作的后续执行中的种子值，并产生输出随机数据; 其中所述一系列操作还包括：确定预定量的新的真实随机数据是否可用; 并且如果这样的数据可用，则根据新的真实随机数据修改至少所得到的值的生成。

6. 发明申请

WO9918668A3 INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路
公开(公告)号：WO9918668A3
公开(公告)日：1999-06-24
申请号：PCT/GB9802963
申请日：1998-10-02
申请人： CAMBRIDGE SILICON RADIO LTD , COLLIER JAMES DIGBY YARLET , SABBERTON IAN MICHAEL
发明人： COLLIER JAMES DIGBY YARLET , SABBERTON IAN MICHAEL
IPC分类号： H03K5/14 , H03K23/54
CPC分类号： H03K23/542
摘要： A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an input signal to be frequency divided, for modulating the propagation delay through each of the amplifier stages about the period of the input signal to be divided, such that when propagation through the odd amplifier stages increases, the propagation through the even amplifier stages decreases. The frequency divider circuit can be used as a pre-scaler of a radio receiver circuit.
摘要翻译：提供了一种分频器电路，其具有与连接到第一放大器级的输入的最后一个放大器级的输出串联的偶数个放大器级; 以及响应于待分频的输入信号的调制装置，用于调制通过每个放大器级的传播延迟，围绕待划分的输入信号的周期，使得当通过奇数放大器级的传播增加时，传播通过甚至放大器级减少。分频器电路可以用作无线电接收机电路的预分频器。

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