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1. 发明申请

WO2006127485A3 METHOD AND SYSTEM FOR INCORPORATION OF PATTERNS AND DESIGN RULE CHECKING 审中-公开
标题翻译：用于加载图案和设计规则检查的方法和系统
公开(公告)号：WO2006127485A3
公开(公告)日：2007-06-21
申请号：PCT/US2006019509
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , NOICE DAVID C
发明人： SCHEFFER LOUIS K , NOICE DAVID C
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes "known good" patterns, which chip fabricators know from experience are successful, and "known bad" patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.
摘要翻译：用于使用模式库代替使用设计规则或除了使用设计规则来表示光刻过程的限制的方法和系统。模式库包括“已知的”模式，哪些芯片制造商从经验中知道是成功的，以及“已知的坏”模式，哪些芯片制造商知道是不成功的。模式库可用于包含指定设计规则的异常，或者完全替换设计规则。在一些实现中，模式库包含统计信息，用于为设计提供整体品质因数。在其他实现中，路由工具可以生成多个可能的IC布局，并且基于包含在模式库中的信息来选择一个IC布局。

2. 发明申请

WO2005109256A3 METHOS AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS 审中-公开
标题翻译：用于设计集成电路的甲板和设备
公开(公告)号：WO2005109256A3
公开(公告)日：2006-05-04
申请号：PCT/US2005014983
申请日：2005-04-29
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K
发明人： SCHEFFER LOUIS K
IPC分类号： G06F17/50 , G03F1/36
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that is calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or data describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, an upper layout for an upper of an IC are modified using information (such a density map) relating to a lower layout for a lower layer of the IC.
摘要翻译：一种使用预制模型库修改IC布局的方法，每个模型包含具有特征的环境，一个或多个几何形状，以及被计算以在晶片上产生令人满意的特征的特征的修改。该模型还可以包含反映一种或多种处理变化的环境的模拟，该环境不反映处理变化和/或重新模拟环境。该模型还可以包含描述作为一个或多个过程变化和/或描述使用布局中特定区域的几何覆盖百分比的调整方程的一个或多个过程变化和/或数据的函数的数据的数据，以确定修改的调整。在一些实施例中，使用与IC的下层的较低布局相关的信息（如密度图）修改IC的上部布局。

3. 发明申请

WO2006127409A3 SYSTEM AND METHOD FOR STATISTICAL DESIGN RULE CHECKING 审中-公开
标题翻译：统计设计规则检查系统与方法
公开(公告)号：WO2006127409A3
公开(公告)日：2007-02-08
申请号：PCT/US2006019305
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K
发明人： SCHEFFER LOUIS K
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.
摘要翻译：允许集成电路设计者指定一个或多个设计规则的方法和系统，并且基于设计规则确定IC设计成功的预期概率。针对每个电路组件编制概率信息，其指定电路组件的特性如果变化时电路组件工作的概率。随着设计规则的检验，每个部件工作的概率被计算出来。将概率相结合以确定IC设计的成功概率。此外，IC设计可以被分成多个部分，并且可以为每个部分分别指定设计规则。这允许设计人员灵活地在IC设计的不同部分使用不同的设计规则。

4. 发明申请

WO0129715A3 DATABASE FOR ELECTRONIC DESIGN AUTOMATION APPLICATIONS 审中-公开
标题翻译：电子设计自动化应用数据库
公开(公告)号：WO0129715A3
公开(公告)日：2002-10-10
申请号：PCT/US0028162
申请日：2000-10-11
申请人： CADENCE DESIGN SYSTEMS INC , DOIG ROBERT C , SCHEFFER LOUIS K
发明人： DOIG ROBERT C , SCHEFFER LOUIS K
IPC分类号： G06F12/00 , G06F17/30 , G06F17/50
CPC分类号： G06F17/30595 , G06F17/30324 , G06F17/30327 , G06F17/50 , Y10S707/99942
摘要： A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given instance within a class. Between classes, individual records in an array may cross-reference, through an array index, records in other arrays. The inherent sequential nature of records stored in the array may be used as linking information, thus avoiding the requirement of storing linking pointers in memory. Rather than storing all of the coordinate or spatial information for a given shape, only the offset information from the preceding shape may be stored, with the assumption that the second shape starts at the ending point of the first shape. Certain default values or characteristics for information within the array records can be assumed unless overridden by an indicator in the array record. Allocation of storage space for data entries may be adaptively managed based on the size of the data to be stored, with allocation size being determined by the largest value of the stored entries, or a header code for the data entry indicating the number of bytes. The data header of each class may include a pointer indicating the position in memory of a main data header, which in turn contains pointers to the positions in memory of the other classes, allowing instances in a class to refer to related instances in the other classes through an integer index number without requiring the use of other pointers.
摘要翻译：用于存储芯片设计信息的数据库包括用于存储特定类别的信息的多个并行阵列。在特定类的一个或多个并行数组上的给定数组索引处开始的相关条目的联合形成类中给定实例的结构。在类之间，数组中的单个记录可以通过数组索引交叉引用其他数组中的记录。存储在阵列中的记录的固有顺序性质可以用作链接信息，因此避免了将链接指针存储在存储器中的需求。不是存储给定形状的所有坐标或空间信息，而是可以存储来自前一形状的偏移信息，假设第二形状从第一形状的终点开始。阵列记录中的信息的某些默认值或特性可以被假设，除非被数组记录中的指示符覆盖。可以基于要存储的数据的大小自适应地管理用于数据条目的存储空间的分配，其中分配大小由所存储的条目的最大值确定，或用于指示字节数的数据条目的标题代码。每个类的数据头可以包括指示主数据头的存储器中的位置的指针，该主数据头还包含指向其他类的存储器中的位置的指针，允许类中的实例引用其他类中的相关实例通过整数索引号，而不需要使用其他指针。

5. 发明申请

WO2005109257A3 METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS 审中-公开
标题翻译：用于设计集成电路的方法和装置
公开(公告)号：WO2005109257A3
公开(公告)日：2005-12-15
申请号：PCT/US2005015024
申请日：2005-04-29
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K
发明人： SCHEFFER LOUIS K
IPC分类号： G03F1/36 , G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including (2205) receiving the upper layout containing features and modifications to features, (2215) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, (2220) selecting a feature in the upper layout, (2225) retrieving, from the density map, the geometry coverage of a sub-region below the feature, (2230) determining a vertical deviation of the feature using the geometry coverage, (2235) determining an alteration to the modification using the vertical deviation, (2240) applying the alteration to the modification and (2245) repeating for all features.
摘要翻译：一种用于使用用于IC的下层的较低布局的信息来修改IC的上层布局的方法，所述方法包括（2205）接收包含特征的上部布局和对特征的修改，（2215），其产生（2220）选择上部布局中的特征，（2225）从密度图检索在特征下方的子区域的几何覆盖度的下部布局的密度图，其具有下部布局的子区域的几何覆盖，（2230）使用所述几何覆盖来确定所述特征的垂直偏差，（2235）使用所述垂直偏差来确定对所述修改的改变，（2240）将所述修改应用于所述修改，并且（2245）针对所有特征进行重复。

6. 发明申请

WO2007147147A2 METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT 审中-公开
标题翻译：用于对置放置对角线的方法和装置
公开(公告)号：WO2007147147A2
公开(公告)日：2007-12-21
申请号：PCT/US2007071397
申请日：2007-06-15
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K
发明人： SCHEFFER LOUIS K
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Some embodiments of the invention provide a method for placing circuit modules in an integrated circuit ("IC") layout. The method computes a placement metric for the IC layout. In some embodiments, computing the placement metric includes partitioning a region the IC layout into several sub-regions by using a cut graph, where the cut graph is an approximation of a diagonal cut line. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut graph. In some embodiments, the cut graph is a staircase cut graph. These staircase cut graphs include several horizontal and vertical cut lines. In some embodiments, the cut graph is a cut arc.
摘要翻译：本发明的一些实施例提供了一种将电路模块放置在集成电路（“IC”）布局中的方法。该方法计算IC布局的布局度量。在一些实施例中，计算布局度量包括通过使用切割图将IC布局的区域划分成若干子区域，其中切割图是对角线切割线的近似。这些实施例然后通过测量由切割图切割的网络的数量来产生拥塞成本估计。在一些实施例中，切割图是梯形切割图。这些楼梯切割图包括几条水平和垂直切割线。在一些实施例中，切割图是切割弧。

7. 发明申请

WO2006127538A3 MANUFACTURING AWARE DESIGN AND DESIGN AWARE MANUFACTURING 审中-公开
标题翻译：制造设计和设计意识制造
公开(公告)号：WO2006127538A3
公开(公告)日：2007-04-05
申请号：PCT/US2006019624
申请日：2006-05-20
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , FUJIMURA AKIRA
发明人： SCHEFFER LOUIS K , FUJIMURA AKIRA
IPC分类号： G06F17/50 , G03C5/00 , G03F1/00 , G06K9/62
CPC分类号： G06F17/5068 , G03F7/70091 , G03F7/70125 , G03F7/70425 , G05B2219/35028 , G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit ("IC") layout (1205). The process receives a manufacturing configuration that specifies a set of manufacturing settings (1210) for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules (1215) based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout (1225). Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit ("IC") (1227). The process receives an IC desig with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings (1230).
摘要翻译：本发明的一些实施例提供了一种用于设计集成电路（“IC”）布局（1205）的制造感知过程。该过程接收制造配置，其指定用于基于IC布局用于制造IC的一组机器的一组制造设置（1210）。该过程基于指定的制造配置来定义一组设计规则（1215）。该过程使用一组设计规则来设计IC布局（1225）。本发明的一些实施例提供了一种用于制造集成电路（“IC”）的设计感知过程（1227）。该过程接收具有相关联的一组设计属性的IC设计。该过程指定制造配置，其指定用于制造IC的一组机器的一组制造设置，其中指定的一组制造设置基于该组设计属性。该过程基于制造设置制造IC（1230）。

8. 发明申请

WO2006127408A3 METHOD AND SYSTEM FOR INCREASED ACCURACY FOR EXTRACTION OF ELECTRICAL PARAMETERS 审中-公开
标题翻译：用于提取电气参数的提高精度的方法和系统
公开(公告)号：WO2006127408A3
公开(公告)日：2007-03-15
申请号：PCT/US2006019304
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , STAUD WOLFGANG H , HUCKABAY JUDY
发明人： SCHEFFER LOUIS K , STAUD WOLFGANG H , HUCKABAY JUDY
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.
摘要翻译：公开了一种改进的方法，系统和计算机程序产品，用于提高IC设计的电参数的精度。一旦制造和平版印刷过程效果被考虑，就按照打印布局的预期几何模型进行提取。这提供了一种更精确的执行提取方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。检查提取的电气参数是否可接受。如果不能接受，则可以修改IC设计以解决任何已识别的问题或对设计的期望改进。

9. 发明申请

WO2006127438A3 METHOD AND SYSTEM FOR CHIP DESIGN USING PHYSICALLY APPROPRIATE COMPONENT MODELS AND EXTRACTION 审中-公开
标题翻译：使用物理特定组件模型和提取的芯片设计方法和系统
公开(公告)号：WO2006127438A3
公开(公告)日：2007-06-07
申请号：PCT/US2006019386
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , PHILLIPS JOEL R
发明人： SCHEFFER LOUIS K , PHILLIPS JOEL R
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009
摘要： An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.
摘要翻译：公开了一种改进的方法，系统和计算机程序产品，用于预测制造中的晶体管的几何模型，并考虑光刻处理效果。这为模拟晶体管提供了更加准确的方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。期望的几何形状包括可以基于布局确定的系统变化以及可以基于平版印刷过程确定的预期随机变化。

10. 发明申请

WO0129715A9 DATABASE FOR ELECTRONIC DESIGN AUTOMATION APPLICATIONS 审中-公开
标题翻译：数字化电子设计自动化应用程序
公开(公告)号：WO0129715A9
公开(公告)日：2002-08-01
申请号：PCT/US0028162
申请日：2000-10-11
申请人： CADENCE DESIGN SYSTEMS INC , DOIG ROBERT C , SCHEFFER LOUIS K
发明人： DOIG ROBERT C , SCHEFFER LOUIS K
IPC分类号： G06F12/00 , G06F17/30 , G06F17/50
CPC分类号： G06F17/30595 , G06F17/30324 , G06F17/30327 , G06F17/50 , Y10S707/99942
摘要： A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given instance within a class. Between classes, individual records in an array may cross-reference, through an array index, records in other arrays. The inherent sequential nature of records stored in the array may be used as linking information, thus avoiding the requirement of storing linking pointers in memory. Rather than storing all of the coordinate or spatial information for a given shape, only the offset information from the preceding shape may be stored, with the assumption that the second shape starts at the ending point of the first shape. Certain default values or characteristics for information within the array records can be assumed unless overridden by an indicator in the array record. Allocation of storage space for data entries may be adaptively managed based on the size of the data to be stored, with allocation size being determined by the largest value of the stored entries, or a header code for the data entry indicating the number of bytes. The data header of each class may include a pointer indicating the position in memory of a main data header, which in turn contains pointers to the positions in memory of the other classes, allowing instances in a class to refer to related instances in the other classes through an integer index number without requiring the use of other pointers.
摘要翻译：用于存储芯片设计信息的数据库包括用于存储特定类别的信息的多个平行阵列。在特定数组索引上开始的相关条目跨特定类的一个或多个并行数组的联合形成了类中给定实例的结构。在类之间，数组中的单个记录可以通过数组索引交叉引用其他数组中的记录。存储在数组中的记录的固有顺序特性可以用作链接信息，从而避免了将链接指针存储在存储器中的需求。而不是存储给定形状的所有坐标或空间信息，只有来自先前形状的偏移信息可以被存储，假定第二形状从第一形状的结束点开始。数组记录中信息的某些默认值或特性可以被假定，除非被数组记录中的指标覆盖。用于数据条目的存储空间的分配可以基于要存储的数据的大小来自适应地管理，其中分配大小由所存储的条目的最大值或者用于指示字节数量的数据条目的头部代码来确定。每个类的数据头可以包括指示主数据头在内存中的位置的指针，该指针又包含指向其他类的存储器中位置的指针，允许类中的实例引用其他类中的相关实例通过一个整数索引号而不需要使用其他指针。

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