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1. 发明申请

WO2004047001A2 METHOD, SYSTEM, AND ARTICLE OF MANUFACTURE FOR IMPLEMENTING METAL-FILL 审中-公开
标题翻译：用于实施金属填充的方法，系统和制造物品
公开(公告)号：WO2004047001A2
公开(公告)日：2004-06-03
申请号：PCT/US2003/036989
申请日：2003-11-19
申请人： CADENCE DESIGN SYSTEMS, INC. , VUONG, Thanh , KAO, William, H. , NOICE, David, C.
发明人： VUONG, Thanh , KAO, William, H. , NOICE, David, C.
IPC分类号： G06K
CPC分类号： G06F17/5068
摘要： Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.
摘要翻译：公开了用于实现用于集成电路的金属填充的单程方法的方法，系统和制品。还公开了用于实现耦合到系留连接的金属填充物的方法，系统和制品。公开的方法包括用于实现具有对应于空白长度的细长形状的金属填充物的方法，系统和制品。还公开了实现与布线方向匹配的金属填充的方面。另一个公开是地点＆amp; 包含集成金属填充机制的路线工具。

2. 发明申请

WO2006127485A3 METHOD AND SYSTEM FOR INCORPORATION OF PATTERNS AND DESIGN RULE CHECKING 审中-公开
标题翻译：用于加载图案和设计规则检查的方法和系统
公开(公告)号：WO2006127485A3
公开(公告)日：2007-06-21
申请号：PCT/US2006019509
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , NOICE DAVID C
发明人： SCHEFFER LOUIS K , NOICE DAVID C
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes "known good" patterns, which chip fabricators know from experience are successful, and "known bad" patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.
摘要翻译：用于使用模式库代替使用设计规则或除了使用设计规则来表示光刻过程的限制的方法和系统。模式库包括“已知的”模式，哪些芯片制造商从经验中知道是成功的，以及“已知的坏”模式，哪些芯片制造商知道是不成功的。模式库可用于包含指定设计规则的异常，或者完全替换设计规则。在一些实现中，模式库包含统计信息，用于为设计提供整体品质因数。在其他实现中，路由工具可以生成多个可能的IC布局，并且基于包含在模式库中的信息来选择一个IC布局。

3. 发明申请

WO2006127485A2 METHOD AND SYSTEM FOR INCORPORATION OF PATTERNS AND DESIGN RULE CHECKING 审中-公开
标题翻译：用于加载图案和设计规则检查的方法和系统
公开(公告)号：WO2006127485A2
公开(公告)日：2006-11-30
申请号：PCT/US2006/019509
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS, INC. , SCHEFFER, Louis, K. , NOICE, David, C.
发明人： SCHEFFER, Louis, K. , NOICE, David, C.
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes "known good" patterns, which chip fabricators know from experience are successful, and "known bad" patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.
摘要翻译：用于使用模式库代替使用设计规则或除了使用设计规则来表示光刻过程的限制的方法和系统。模式库包括“已知的”模式，哪些芯片制造商从经验中知道是成功的，以及“已知的坏”模式，哪些芯片制造商知道是不成功的。模式库可用于包含指定设计规则的异常，或者完全替换设计规则。在一些实现中，模式库包含统计信息，用于为设计提供整体品质因数。在其他实现中，路由工具可以生成多个可能的IC布局，并且基于包含在模式库中的信息来选择一个IC布局。

4. 发明申请

WO2004047001A3 METHOD, SYSTEM, AND ARTICLE OF MANUFACTURE FOR IMPLEMENTING METAL-FILL 审中-公开
标题翻译：用于实施金属膜的制造方法，系统和制品
公开(公告)号：WO2004047001A3
公开(公告)日：2004-09-23
申请号：PCT/US0336989
申请日：2003-11-19
申请人： CADENCE DESIGN SYSTEMS INC , VUONG THANH , KAO WILLIAM H , NOICE DAVID C
发明人： VUONG THANH , KAO WILLIAM H , NOICE DAVID C
IPC分类号： G06F17/50 , G06K20060101
CPC分类号： G06F17/5068
摘要： Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.
摘要翻译：公开了用于实现用于集成电路的金属填充的单程方法的方法，系统和制品。还公开了一种用于实现耦合到连接连接的金属填充的方法，系统和制品。公开的方法包括用于实现具有对应于空白长度的细长形状的金属填充物的方法，系统和制品。还公开了实现与路由方向匹配的金属填充的方面。另一个公开内容是结合了集成金属填充机构的布置和布线工具的实现。

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