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1. 发明申请

WO2008045411A2 ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE 审中-公开
标题翻译：用于存储器装置的充电泵电路中的空闲状态的自适应调节器
公开(公告)号：WO2008045411A2
公开(公告)日：2008-04-17
申请号：PCT/US2007/021534
申请日：2007-10-09
申请人： ATMEL CORPORATION , PASSERINI, Marco , SIVERO, Stefano , SACCO, Andrea , MARZIANI, Monica
发明人： PASSERINI, Marco , SIVERO, Stefano , SACCO, Andrea , MARZIANI, Monica
IPC分类号： G11C5/14 , G11C16/04 , G11C7/00 , G11C7/02 , G11C11/34
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

2. 发明申请

WO2004077439A2 AN APPARATUS AN METHOD FOR A CONFIGURABLE MIRROR FAST SENSE AMPLIFIER 审中-公开
标题翻译：一种用于可配置反射镜快速感测放大器的装置
公开(公告)号：WO2004077439A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/004729
申请日：2004-02-17
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
IPC分类号： G11C
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063 , G11C2207/2254
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译：用于闪存的可配置镜像读出放大器系统具有以下特征。电源产生参考电压。多个晶体管偏置在参考电压。多个晶体管各自耦合到第二晶体管。多个晶体管中的每一个还被配置为提供用于与闪存进行比较的电流。参考电压是内部的，稳定的并且与电源或温度的变化无关。多个晶体管彼此并联。镜像晶体管被耦合到多个晶体管。多个晶体管被配置为使得至少一个晶体管中的至少一个晶体管被信号激活以提供用于与闪存进行比较的电流。此外，参考电压可能会修改，以修改电流以与闪存进行比较。

3. 发明申请

WO2006044163A2 SYSTEM AND METHOD FOR AVOIDING OFFSET IN AND REDUCING THE FOOTPRINT OF A NON-VOLATILE MEMORY 审中-公开
标题翻译：避免偏差和减少非易失性存储器容量的系统和方法
公开(公告)号：WO2006044163A2
公开(公告)日：2006-04-27
申请号：PCT/US2005/035166
申请日：2005-10-03
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , RIVA REGGIORI, Riccardo , SACCO, Andrea , FIGINI, Luca
发明人： FRULIO, Massimiliano , RIVA REGGIORI, Riccardo , SACCO, Andrea , FIGINI, Luca
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
摘要翻译：一种用于避免偏移并减小具有多个存储器组电路的非易失性存储器的占位面积的系统和方法。每个存储体电路具有耦合到读出放大器，耦合到存储器单元的行和列解码器以及耦合到读出放大器的偏置电路的存储单元。该系统包括耦合到多个存储体电路中的每一个的参考单元矩阵。参考单元矩阵被配置为为多个存储体电路中的每一个提供参考单元电流。

4. 发明申请

WO2006135658A2 SYSTEM AND METHOD FOR MATCHING RESISTANCE IN A NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：WO2006135658A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/022220
申请日：2006-06-07
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , SACCO, Andrea , ODDONE, Giorgio , BARTOLI, Simone
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , ODDONE, Giorgio , BARTOLI, Simone
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

5. 发明申请

WO2008076553A2 A NEW IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 审中-公开
标题翻译：具有高写并发性的闪存存储器的冗余冗余的新实现
公开(公告)号：WO2008076553A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/084460
申请日：2007-11-12
申请人： ATMEL CORPORATION , BARTOLI, Simone , SURICO, Stefano , SACCO, Andrea , MOSTOLA, Maria
发明人： BARTOLI, Simone , SURICO, Stefano , SACCO, Andrea , MOSTOLA, Maria
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array (300) has r columns of redundant memory cells (306), r redundant senses (312), and a redundant column decoder (308). Redundant address registers (332) store addresses of defective regular memory cells. Redundant latches (338) are provided in n groups of r latches. Redundancy comparison logic (330) compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal (333) to disable the regular senses (310) for one of the n groups of m columns, an ENABLE_LATCH signal (334) to one of the n groups of m columns to disable corresponding regular senses, and one of r REDO signals (336) to a respective one of the r redundant latches (338) in one of the n groups that is disabled. The selected one of the redundant latches (338) activates one of the r redundant senses (312) to access a redundant column.
摘要翻译：冗余存储器阵列（300）具有r列的冗余存储器单元（306），r冗余感测（312）和冗余列解码器（308）。冗余地址寄存器（332）存储有缺陷的常规存储单元的地址。冗余锁存器（338）设置在n组r个锁存器中。冗余比较逻辑（330）将缺陷规则存储器单元的地址与外部输入地址进行比较。如果比较是真实的，则提供的是：禁用n列m列中的一个的常规感测（310）的DISABLE_LOAD信号（333），到m列的n组之一的ENABLE_LATCH信号（334）禁用相应的常规感测，并且将r个REDO信号中的一个（336）禁止到被禁用的n个组中的一个中的r个冗余锁存器（338）中的相应一个。所选择的冗余锁存器（338）中的一个激活r个冗余感测（312）中的一个以访问冗余列。

6. 发明申请

WO2008057835A2 LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL 审中-公开
标题翻译：低电压柱解码器共享存储阵列P-WELL
公开(公告)号：WO2008057835A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/082875
申请日：2007-10-29
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , SURICO, Stefano , SACCO, Andrea , MANFRE, Davide
发明人： FRULIO, Massimiliano , SURICO, Stefano , SACCO, Andrea , MANFRE, Davide
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays (302A - 302X) are formed in a p-well region (304). Each of the memory sub-arrays (302A - 302X) has at least one first-level column decoder (306A - 306X) that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder (316) is formed outside of the p-well region (304) and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers (320). During a memory erase mode of operation, a high voltage is provided to bias the p-well region (304) and a plurality of high-voltage switches (326A - 326X) are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders (306A - 306X). One or more intermediate-level column decoders (312) are formed as low-voltage selector transistors in the p-well (304) between the first-level column decoder (306A - 306X) and the last-level column decoder (316). Each of the intermediate- level column decoders (312) also has a high-voltage switch (326Y) that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate- level column decoders (312).
摘要翻译：多个存储器子阵列（302A-302X）形成在p阱区域（304）中。每个存储子阵列（302A-302X）具有至少一个第一级解码器（306A-306X），其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器（316）形成在p阱区域（304）的外部，并且包括高压MOS晶体管，以向读出放大器（320）阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域（304），并且激活多个高压开关（326A-326X）以向选择器晶体管的栅极端提供高电压在第一级列解码器（306A-306X）中。在第一级列解码器（306A-306X）和最后级列解码器（316）之间的p阱（304）中形成一个或多个中间级列解码器（312）作为低电压选择晶体管。每个中间级列解码器（312）还具有在存储器擦除操作模式期间被激活以向中间级列解码器（312）的栅极端提供高电压的高压开关（326Y）。

7. 发明申请

WO2006058134A3 METHOD AND SYSTEM FOR REGULATING A PROGRAM VOLTAGE VALUE DURING MULTILEVEL MEMORY DEVICE PROGRAMMING 审中-公开
公开(公告)号：WO2006058134A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/042570
申请日：2005-11-23
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , BARTOLI, Simone , MANFRÉ, David , SACCO, Andrea
发明人： FRULIO, Massimiliano , BARTOLI, Simone , MANFRÉ, David , SACCO, Andrea
IPC分类号： G11C16/04
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.

8. 发明申请

WO2004027831A3 FAST DYNAMIC LOW-VOLTAGE CURRENT MIRROR WITH COMPENSATED ERROR 审中-公开
公开(公告)号：WO2004027831A3
公开(公告)日：2004-04-01
申请号：PCT/US2003/029793
申请日：2003-09-17
申请人： ATMEL CORPORATION
发明人： BEDARIDA, Lorenzo , MANEA, Danut , MARSELLA, Mirella , SACCO, Andrea
IPC分类号： H03K3/01
摘要： A current mirror comprises a current source (10); a first n-channel MOS transistor (12) having a drain and a gate coupled to the current source and a source coupled to a source potential; a second n-channel MOS transistor (14) having a drain, a gate coupled, to the drain and a gate of the first n-channel MOS transistor, and a source coupled to the source potential; and a zero- threshold-voltage MOS transistor (28) having a source coupled to the drain of the second n-channel MOS transistor, a gate coupled to the drain and a gate of the first n-channel MOS transistor and a drain comprising an output-current node.

9. 发明申请

WO2004025656A2 FAST DYNAMIC MIRROR SENSE AMPLIFIER WITH SEPARATE COMPARISON EQUALIZATION AND EVALUATION PATHS 审中-公开
标题翻译：具有单独比较均衡和评估的快速动态镜像放大器
公开(公告)号：WO2004025656A2
公开(公告)日：2004-03-25
申请号：PCT/US2003/028814
申请日：2003-09-11
申请人： ATMEL CORPORATION
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , MARSELLA, Mirella , FRULIO, Massimiliano
IPC分类号： G11C
CPC分类号： G11C7/067 , G11C7/062 , G11C7/14
摘要： A memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate.
摘要翻译：用于感测来自存储器单元的数据的存储单元感测电路包括耦合以传递参考电流的参考存储单元。读出放大器具有耦合到数据存储单元的偏置电路的第一输入和第二输入。第一镜将参考电流反射到耦合到读出放大器的第一输入端的电压。第二镜将参考电流反射到耦合到数据存储单元的偏置电路的电压。第三反射镜将参考电流反射到通过传输门耦合到读出放大器的第二输入的电压。

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