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1. 发明申请

WO2022240567A1 MULTI-PORT EXHAUST SYSTEM FOR EPITAXIAL DEPOSITION CHAMBER 审中-公开
公开(公告)号：WO2022240567A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/025772
申请日：2022-04-21
申请人： APPLIED MATERIALS, INC.
发明人： ISHIKAWA, Tetsuya , SRINIVASAN, Swaminathan T. , BAUER, Matthias , SUBBANNA, Manjunath , MORADIAN, Ala , SHAH, Kartik Bhupendra , SANCHEZ, Errol Antonio C. , RICE, Michael R. , REIMER, Peter , SHULL, Marc
IPC分类号： C30B25/14 , C30B25/12 , C30B25/10 , C23C16/44 , C23C16/48 , C30B25/165 , H01L21/67115 , H01L21/6719
摘要： Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body, across the substrate, and to an upper gas outlet on a second side of the chamber body, flowing a purge gas from a lower gas inlet on the first side of the chamber body, across the lower surface of the susceptor, and to a lower gas outlet on the second side of the chamber body, and maintaining a pressure of the lower chamber region greater than a pressure of the upper chamber region.

2. 发明申请

WO2016007340A1 ATOMIC LAYER EPITAXY FOR SEMICONDUCTOR GATE STACK LAYER FOR ADVANCED CHANNEL DEVICES 审中-公开
标题翻译：用于高级通道器件的半导体栅极堆叠层的原子层外观
公开(公告)号：WO2016007340A1
公开(公告)日：2016-01-14
申请号：PCT/US2015/038752
申请日：2015-07-01
申请人： APPLIED MATERIALS, INC.
发明人： SRINIVASAN, Swaminathan T. , HUNTER, Aaron Muir , BAUER, Matthias , SADE, Amikam
IPC分类号： H01L21/205
CPC分类号： H01L21/02658 , C23C16/4412 , C23C16/45544 , C23C16/46 , C23C16/483 , H01L21/0262 , H01L21/02661 , H01L21/02686 , H01L21/268 , H01L21/67028 , H01L21/67115 , H01L21/68742 , H01L21/68792
摘要： Embodiments of the present disclosure provide methods and apparatus for forming an epitaxial layer on a substrate. The substrate is exposed to pulsed laser radiation to clean, anneal, and/or activate the surface of the substrate. The substrate is then exposed to a deposition precursor in a self-limiting deposition process. The substrate may again be exposed to pulsed laser radiation, and then exposed to a second deposition precursor in a second self-limiting deposition process. The process may be repeated as desired to form an epitaxial layer of very high quality one atomic layer at a time.
摘要翻译：本公开的实施例提供了用于在衬底上形成外延层的方法和装置。将衬底暴露于脉冲激光辐射以清洁，退火和/或激活衬底的表面。然后将衬底在自限制沉积工艺中暴露于沉积前体。衬底可以再次暴露于脉冲激光辐射，然后在第二自限制沉积工艺中暴露于第二沉积前体。可以根据需要重复该过程，以一次形成非常高质量的一个原子层的外延层。

3. 发明申请

WO2017196482A1 FORMING NON-LINE-OF-SIGHT SOURCE DRAIN EXTENSION IN AN NMOS FINFET USING N-DOPED SELECTIVE EPITAXIAL GROWTH 审中-公开
标题翻译：利用N掺杂选择性外延生长在NMOS FinFET中形成非线性源漏极扩展
公开(公告)号：WO2017196482A1
公开(公告)日：2017-11-16
申请号：PCT/US2017/027156
申请日：2017-04-12
申请人： APPLIED MATERIALS, INC.
发明人： GOSSMANN, Hans-Joachim Ludwig , COLOMBEAU, Benjamin , BAUER, Matthias
IPC分类号： H01L29/66 , H01L29/78
摘要： A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
摘要翻译： finFET器件包括n型掺杂源极和/或漏极延伸部分，其设置在鳍式场效应晶体管的栅极间隔物与半导体衬底的体上半导体部分之间，其上形成n掺杂源极或漏极扩展处理。通过选择性外延生长（SEG）工艺在形成于栅极间隔物附近的空腔中形成n掺杂源极或漏极延伸区。

4. 发明申请

WO2021081155A1 METHODS FOR GAA I/O FORMATION BY SELECTIVE EPI REGROWTH 审中-公开
公开(公告)号：WO2021081155A1
公开(公告)日：2021-04-29
申请号：PCT/US2020/056768
申请日：2020-10-22
申请人： APPLIED MATERIALS, INC.
发明人： COLOMBEAU, Benjamin , BAUER, Matthias , SIDDIQUI, Naved Ahmed , STOUT, Phillip
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/423 , H01L27/088 , H01L29/786 , H01L29/78
摘要： Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

5. 发明申请

WO2018067191A1 MULTI-CHANNEL FLOW RATIO CONTROLLER AND PROCESSING CHAMBER 审中-公开
标题翻译：多通道流量比例控制器和处理室
公开(公告)号：WO2018067191A1
公开(公告)日：2018-04-12
申请号：PCT/US2017/015475
申请日：2017-01-27
申请人： APPLIED MATERIALS, INC.
发明人： BAUER, Matthias
IPC分类号： H01L21/205 , H01L21/687 , H01L21/02 , H01L21/67
摘要： Implementations of the present disclosure generally relate to one or more flow ratio controllers and one or more gas injection inserts in the semiconductor processing chamber. In one implementation, an apparatus includes a first flow ratio controller including a first plurality of flow controllers, a second flow ratio controller including a second plurality of flow controllers, and a gas injection insert including a first portion and a second portion. The first portion includes a first plurality of channels and the second portion includes a second plurality of channels. The apparatus further includes a plurality of gas lines connecting the first and second pluralities of flow controllers to the first and second pluralities of channels. One or more gas lines of the plurality of gas lines are each connected to a channel of the first plurality of channels and a channel of the second plurality of channels.
摘要翻译：本公开的实施方式通常涉及半导体处理室中的一个或多个流量比率控制器和一个或多个气体注入插入件。在一个实施方式中，一种装置包括包含第一多个流量控制器的第一流量比率控制器，包括第二多个流量控制器的第二流量比率控制器以及包括第一部分和第二部分的气体注入插入件。第一部分包括第一多个通道，第二部分包括第二多个通道。该设备还包括将第一和第二多个流量控制器连接到第一和第二多个通道的多条气体管线。多根气体管线中的一根或多根气体管线各自连接到第一多个通道的通道和第二多个通道的通道。

6. 发明申请

WO2018052473A2 CONTACT INTEGRATION AND SELECTIVE SILICIDE FORMATION METHODS 审中-公开
标题翻译：接触集成和选择性硅化物形成方法
公开(公告)号：WO2018052473A2
公开(公告)日：2018-03-22
申请号：PCT/US2017/015121
申请日：2017-01-26
申请人： APPLIED MATERIALS, INC.
发明人： BAUER, Matthias
摘要： Methods for selective silicide formation are described herein. The methods are generally utilized in conjunction with contact structure integration schemes and provide for improved silicide formation characteristics. In one implementation, a silicide material is selectively formed on source/drain (S/D) regions at a temperature less than about 550°C. The resulting silicide is believed to exhibit desirable contact resistance and applicability in advanced contact integration schemes.
摘要翻译：本文描述了用于选择性硅化物形成的方法。这些方法通常与触点结构集成方案结合使用并提供改进的硅化物形成特性。在一个实施方式中，在小于约550℃的温度下在源极/漏极（S / D）区域上选择性地形成硅化物材料。据认为，所得到的硅化物在先进的触点集成方案中表现出理想的接触电阻和适用性。

7. 发明申请

WO2022240574A1 MULTI-ZONE LAMP HEATING AND TEMPERATURE MONITORING IN EPITAXY PROCESS CHAMBER 审中-公开
公开(公告)号：WO2022240574A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/026071
申请日：2022-04-23
申请人： APPLIED MATERIALS, INC.
发明人： ISHIKAWA, Tetsuya , SRINIVASAN, Swaminathan T. , SHAH, Kartik Bhupendra , MORADIAN, Ala , SUBBANNA, Manjunath , BAUER, Matthias , REIMER, Peter , RICE, Michael R.
IPC分类号： C30B25/10 , C30B25/16 , C23C16/44 , C23C16/48 , C30B25/14 , C30B25/165 , H01L21/67115 , H01L21/6719
摘要： The present disclosure generally relates to an epitaxial chamber for processing of semiconductor substrates. In one example, the epitaxial chamber has a chamber body assembly. The chamber body assembly includes a lower window and an upper window, wherein chamber body assembly, the lower window and the upper window enclose an internal volume. A susceptor assembly is disposed in the internal volume. The epitaxial chamber also has a plurality of temperature control elements. The plurality of temperature control elements include one or more of an upper lamp module, a lower lamp module, an upper heater, a lower heater, or a heated gas passage.

8. 发明申请

WO2022240560A1 CHAMBER ARCHITECTURE FOR EPITAXIAL DEPOSITION AND ADVANCED EPITAXIAL FILM APPLICATIONS 审中-公开
公开(公告)号：WO2022240560A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/025540
申请日：2022-04-20
申请人： APPLIED MATERIALS, INC.
发明人： ISHIKAWA, Tetsuya , SRINIVASAN, Swaminathan T. , SHAH, Kartik Bhupendra , MORADIAN, Ala , SUBBANNA, Manjunath , BAUER, Matthias , REIMER, Peter , RICE, Michael R.
IPC分类号： C30B25/10 , C30B25/14 , C30B25/16 , H01L21/67 , C23C16/44 , C23C16/48 , C30B25/165 , H01L21/67115 , H01L21/6719
摘要： The present disclosure generally relates to a process chamber for processing of semiconductor substrates. The process chamber includes an upper lamp assembly, a lower lamp assembly, a substrate support, an upper window disposed between the substrate support and the upper lamp assembly, a lower window disposed between the lower lamp assembly and the substrate support, an inject ring, and a base ring. Each of the upper lamp assembly and the lower lamp assembly include vertically oriented lamp apertures for the placement of heating lamps therein. The inject ring includes gas injectors disposed therethrough and the base ring includes a substrate transfer passage, a lower chamber exhaust passage, and one or more upper chamber exhaust passages. The gas injectors are disposed over the substrate transfer passage and across from the lower chamber exhaust passage and the one or more upper chamber exhaust passages.

9. 发明申请

WO2022240553A1 GAS INJECTOR FOR EPITAXY AND CVD CHAMBER 审中-公开
公开(公告)号：WO2022240553A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/025321
申请日：2022-04-19
申请人： APPLIED MATERIALS, INC.
发明人： ISHIKAWA, Tetsuya , SRINIVASAN, Swaminathan T. , BAUER, Matthias , MORADIAN, Ala , SUBBANNA, Manjunath , SHAH, Kartik Bhupendra , SANCHEZ, Errol Antonio C. , ZOKAEI, Sohrab , RICE, Michael R. , REIMER, Peter
IPC分类号： C30B25/14 , C30B25/10 , C30B25/16 , C23C16/44 , C23C16/48 , C30B25/165 , H01L21/67115 , H01L21/6719
摘要： The present disclosure generally relates to gas inject apparatus for a process chamber for processing of semiconductor substrates. The gas inject apparatus include one or more gas injectors which are configured to be coupled to the process chamber. Each of the gas injectors are configured to receive a process gas and distribute the process gas across one or more gas outlets. The gas injectors include a plurality of pathways, a fin array, and a baffle array. The gas injectors are individually heated. A gas mixture assembly is also utilized to control the concentration of process gases flown into a process volume from each of the gas injectors. The gas mixture assembly enables the concentration as well as the flow rate of the process gases to be controlled.

10. 发明申请

WO2020010299A1 INTEGRATED CMOS SOURCE DRAIN FORMATION WITH ADVANCED CONTROL 审中-公开
公开(公告)号：WO2020010299A1
公开(公告)日：2020-01-09
申请号：PCT/US2019/040677
申请日：2019-07-05
申请人： APPLIED MATERIALS, INC.
发明人： COLOMBEAU, Benjamin , MANDREKAR, Tushar , LIU, Patricia M. , PARIKH, Suketu Arun , BAUER, Matthias , KIOUSSIS, Dimitri R. , NATARAJAN, Sanjay , DUBE, Abhishek
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8238 , H01L21/02 , H01L21/3065 , H01L21/677 , H01L21/67
摘要： A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

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