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1. 发明申请

WO2019222320A1 ATOMIC LAYER SELF ALIGNED SUBSTRATE PROCESSING AND INTEGRATED TOOLSET 审中-公开
公开(公告)号：WO2019222320A1
公开(公告)日：2019-11-21
申请号：PCT/US2019/032373
申请日：2019-05-15
申请人： APPLIED MATERIALS, INC.
发明人： PARIKH, Suketu Arun
IPC分类号： C23C16/455 , C23C16/54 , C23C16/56 , C23C16/458 , H01L21/687 , H01L21/67
摘要： Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.

2. 发明申请

WO2020176502A1 A FILM STACK FOR LITHOGRAPHY APPLICATIONS 审中-公开
公开(公告)号：WO2020176502A1
公开(公告)日：2020-09-03
申请号：PCT/US2020/019696
申请日：2020-02-25
申请人： APPLIED MATERIALS, INC.
发明人： TEJINDER, Singh , PARIKH, Suketu Arun , DIEHL, Daniel Lee , STOLFI, Michael Anthony , RAMALINGAM, Jothilingam , CAO, Yong , YAN, Lifan , LANG, Chi-I , HWANG, Ho-yung David
IPC分类号： H01L21/033 , H01L21/311
摘要： Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

3. 发明申请

WO2013162720A1 CONTACT AND INTERCONNECT METALLIZATION FOR SOLAR CELLS 审中-公开
标题翻译：用于太阳能电池的接触和互连金属化
公开(公告)号：WO2013162720A1
公开(公告)日：2013-10-31
申请号：PCT/US2013/030000
申请日：2013-03-08
申请人： APPLIED MATERIALS, INC. , PARIKH, Suketu Arun , SHU, Jen , GEE, James, M.
发明人： PARIKH, Suketu Arun , SHU, Jen , GEE, James, M.
IPC分类号： H01L31/18 , H01L31/042 , H01L31/0216 , H01L31/0236
CPC分类号： H01L31/1864 , H01L21/67155 , H01L31/02167 , H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521 , Y10T29/41
摘要： A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.
摘要翻译：制造线包括被配置为纹理衬底的纹理化模块，被配置为形成发射极区域的发射器模块，被配置为形成钝化层的钝化层模块，被配置为形成屏障接触区域的阻挡接触模块，被配置为将所述阻挡接触区域退火，配置成形成顶部金属接触区域的顶部金属接触模块以及被配置为将所述阻挡接触区域焊接到所述顶部金属接触区域的焊接模块。这些模块由一个或多个自动衬底处理器集成到单个制造线中。一种制造太阳能电池的方法包括在自动化生产线中依次进行：在衬底中掺杂掺杂剂; 设置钝化层; 处理和退火阻挡金属浆料以形成屏障接触; 并且配置和退火金属接触膏以形成顶部金属接触区域。

4. 发明申请

WO2023034477A1 SELF-ALIGNED WIDE BACKSIDE POWER RAIL CONTACTS TO MULTIPLE TRANSISTOR SOURCES 审中-公开
公开(公告)号：WO2023034477A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/042301
申请日：2022-09-01
申请人： APPLIED MATERIALS, INC.
发明人： PARIKH, Suketu Arun , PAL, Ashish , BAZIZI, El Mehdi , YEOH, Andrew , INGLE, Nitin K. , SUNDARRAJAN, Arvind , SEE, Guan Huei , BERKENS, Martinus Maria , DESHPANDE, Sameer A. , PRANATHARTHIHARAN, Balasubramanian , YANG, Yen-Chu
IPC分类号： H01L21/8234 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/423 , H01L29/66
摘要： Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

5. 发明申请

WO2023034476A1 METHOD OF ULTRA THINNING OF WAFER 审中-公开
公开(公告)号：WO2023034476A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/042300
申请日：2022-09-01
申请人： APPLIED MATERIALS, INC.
发明人： PARIKH, Suketu Arun , PAL, Ashish , BAZIZI, El Mehdi , YEOH, Andrew , INGLE, Nitin K. , SUNDARRAJAN, Arvind , SEE, Guan Huei , BERKENS, Martinus Maria , DESHPANDE, Sameer A. , PRANATHARTHIHARAN, Balasubramanian , YANG, Yen-Chu
IPC分类号： H01L21/8234 , H01L21/18 , H01L23/528 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/66
摘要： Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

6. 发明申请

WO2020077185A1 STACKED TRANSISTOR DEVICE 审中-公开
公开(公告)号：WO2020077185A1
公开(公告)日：2020-04-16
申请号：PCT/US2019/055799
申请日：2019-10-11
申请人： APPLIED MATERIALS, INC.
发明人： PARIKH, Suketu Arun , NATARAJAN, Sanjay
IPC分类号： H01L27/088 , H01L29/423 , H01L29/66 , H01L29/732
摘要： Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors are separated from adjacent layers by a horizontal isolation layer.

7. 发明申请

WO2023034478A1 BACKSIDE POWER RAIL TO DEEP VIAS 审中-公开
公开(公告)号：WO2023034478A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/042302
申请日：2022-09-01
申请人： APPLIED MATERIALS, INC.
发明人： PARIKH, Suketu Arun , PAL, Ashish , BAZIZI, El Mehdi , YEOH, Andrew , INGLE, Nitin K. , SUNDARRAJAN, Arvind , SEE, Guan Huei , BERKENS, Martinus Maria , DESHPANDE, Sameer, A. , PRANATHARTHIHARAN, Balasubramanian , YANG, Yen-Chu
IPC分类号： H01L21/8234 , H01L21/18 , H01L21/768 , H01L23/528 , H01L23/532 , H01L29/423
摘要： Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

8. 发明申请

WO2022076277A1 LOW RESISTANCE AND HIGH RELIABILITY METALLIZATION MODULE 审中-公开
公开(公告)号：WO2022076277A1
公开(公告)日：2022-04-14
申请号：PCT/US2021/053304
申请日：2021-10-04
申请人： APPLIED MATERIALS, INC.
发明人： SHAVIV, Roey , PARIKH, Suketu Arun , CHEN, Feng , CHEN, Lu
IPC分类号： H01L21/768 , H01L21/285 , H01L21/67 , C23C16/54
摘要： Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

9. 发明申请

WO2021242355A1 METHODS OF MODIFYING PORTIONS OF LAYER STACKS 审中-公开
公开(公告)号：WO2021242355A1
公开(公告)日：2021-12-02
申请号：PCT/US2021/021916
申请日：2021-03-11
申请人： APPLIED MATERIALS, INC.
发明人： PARIKH, Suketu Arun
IPC分类号： H01L21/768 , H01L21/311
摘要： Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

10. 发明申请

WO2020176181A1 A FILM STACK FOR LITHOGRAPHY APPLICATIONS 审中-公开
公开(公告)号：WO2020176181A1
公开(公告)日：2020-09-03
申请号：PCT/US2020/015182
申请日：2020-01-27
申请人： APPLIED MATERIALS, INC.
发明人： TEJINDER, Singh , PARIKH, Suketu Arun , DIEHL, Daniel Lee , STOLFI, Michael Anthony , RAMALINGAM, Jothilingam , CAO, Yong , YAN, Lifan , LANG, Chi-I , HWANG, Ho-yung David
IPC分类号： H01L21/033
摘要： Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one embodiment, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, wherein the hardmask layer comprises a metal containing material having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

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