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1. 发明申请

WO2022081450A1 SYSTEMS AND METHODS FOR ANALYZING DEFECTS IN CVD FILMS 审中-公开
公开(公告)号：WO2022081450A1
公开(公告)日：2022-04-21
申请号：PCT/US2021/054356
申请日：2021-10-11
申请人： APPLIED MATERIALS, INC.
发明人： PANDIT, Mandar B. , CAI, Man-Ping , LI, Wenhui , TSIANG, Michael , JHA, Praket , LENG, Jingmin
IPC分类号： H01L21/66 , H01L21/02 , G01N21/95 , C23C16/40 , C23C16/52 , C23C16/56
摘要： Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.

2. 发明申请

WO2022245641A1 FLOWABLE CVD FILM DEFECT REDUCTION 审中-公开
公开(公告)号：WO2022245641A1
公开(公告)日：2022-11-24
申请号：PCT/US2022/029125
申请日：2022-05-13
申请人： APPLIED MATERIALS, INC.
发明人： LI, Wenhui , JHA, Praket P. , PANDIT, Mandar B. , CAI, Man-Ping , LIANG, Jingmei , TSIANG, Michael Wenyoung
IPC分类号： C23C16/04 , C23C16/40 , C23C16/56 , C23C16/02 , C23C16/46
摘要： Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.

3. 发明申请

WO2014149281A1 LAYER-BY-LAYER DEPOSITION OF CARBON-DOPED OXIDE FILMS 审中-公开
标题翻译：碳掺杂氧化膜的层叠沉积
公开(公告)号：WO2014149281A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/016604
申请日：2014-02-14
申请人： APPLIED MATERIALS, INC.
发明人： BEHERA, Swayambhu P. , SHAIKH, Shahid , MANNA, Pramit , PANDIT, Mandar B. , SUMMAN, Tersem , REILLY, Patrick , PADHI, Deenesh , KIM, Bok Hoen , PARK, Heung Lak , WITTY, Derek R.
IPC分类号： H01L21/31
CPC分类号： H01L21/02115 , C23C16/26 , C23C16/50 , H01L21/02274 , H01L21/0337 , H01L21/31116
摘要： Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source : plasma-initiating gas : dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300C to about 500C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features.
摘要翻译：本发明的实施方案涉及保形碳基材料的沉积。在一个实施例中，该方法包括在衬底上沉积具有预定厚度的牺牲电介质层，通过去除牺牲电介质层的部分以暴露衬底的上表面，引入烃源，等离子体 - 引发气体和稀释气体进入处理室，其中烃源的体积流量：等离子体引发气体：稀释气体的比例为1:0.5:20，在约300℃的沉积温度下产生等离子体至约500℃，以在图案化特征和暴露的基底的上表面上沉积共形无定形碳层，从图案化特征的上表面和基底的上表面选择性去除无定形碳层，并且去除图案化特征。

4. 发明申请

WO2011028349A3 REMOTE HYDROGEN PLASMA SOURCE OF SILICON CONTAINING FILM DEPOSITION 审中-公开
公开(公告)号：WO2011028349A3
公开(公告)日：2011-03-10
申请号：PCT/US2010/044133
申请日：2010-08-02
申请人： APPLIED MATERIALS, INC. , YUAN, Zheng , PANDIT, Mandar B. , SCHMITT, Francimar C. , ZHENG, Yi , YANG, Fan , LI, Lipan , TSO, Alan , HO, Dustin W. , CHO, Tom K. , THAKUR, Randhir
发明人： YUAN, Zheng , PANDIT, Mandar B. , SCHMITT, Francimar C. , ZHENG, Yi , YANG, Fan , LI, Lipan , TSO, Alan , HO, Dustin W. , CHO, Tom K. , THAKUR, Randhir
IPC分类号： H01L21/205 , H01L21/336 , H01L31/042
摘要： Methods for forming and treating a silicon containing layer in a thin film transistor structure or solar cell devices are provided. In one embodiment, a method for forming a silicon containing layer on a substrate includes providing a substrate into a processing chamber, providing a gas mixture having a silicon containing gas into the processing chamber, providing a hydrogen containing gas from a remote plasma source coupled to the processing chamber, applying a RF power less than 17.5 mWatt/cm 2 to the processing chamber, and forming a silicon containing layer on the substrate.

5. 发明申请

WO2016111811A1 SELF-ALIGNED PROCESS 审中-公开
标题翻译：自对准过程
公开(公告)号：WO2016111811A1
公开(公告)日：2016-07-14
申请号：PCT/US2015/065719
申请日：2015-12-15
申请人： APPLIED MATERIALS, INC
发明人： PANDIT, Mandar B. , WANG, Anchuan , INGLE, Nitin K.
IPC分类号： H01L21/68
CPC分类号： H01J37/32412 , H01J37/32357 , H01L21/3065 , H01L21/31116 , H01L21/31155 , H01L21/76825 , H01L21/76897
摘要： Methods of forming self-aligned structures on patterned substrates are described. The methods may be used to form metal lines or vias without the use of a separate photolithography pattern definition operation. Self-aligned contacts may be produced regardless of the presence of spacer elements. The methods include directionally ion-implanting a gapfill portion of a gapfill silicon oxide layer to implant into the gapfill portion without substantially ion-implanting the remainder of the gapfill silicon oxide layer (the sidewalls). Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that the gapfill portions of silicon oxide are selectively etched relative to other exposed portions exposed parallel to the ion implantation direction. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.
摘要翻译：描述了在图案化衬底上形成自对准结构的方法。该方法可用于形成金属线或通孔而不使用单独的光刻图案定义操作。可以产生自对准的触点，而不管间隔元件的存在。所述方法包括定向地离子注入间隙填充氧化硅层的间隙填充部分以注入到间隙填充部分中，而基本上不离子注入间隙填充氧化硅层（侧壁）的剩余部分。随后，使用含氟前体形成远程等离子体以蚀刻图案化衬底，使得相对于平行于离子注入方向暴露的其它暴露部分选择性地蚀刻氧化硅的间隙填充部分。在没有离子注入的情况下，蚀刻操作将是各向同性的，这是由于在蚀刻过程期间等离子体激发的远端特性。

6. 发明申请

WO2015060929A1 METHODS FOR PATTERNING A HARDMASK LAYER FOR AN ION IMPLANTATION PROCESS 审中-公开
标题翻译：用于绘制离子植入过程的HARDMASK层的方法
公开(公告)号：WO2015060929A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/051938
申请日：2014-08-20
申请人： APPLIED MATERIALS, INC.
发明人： WOOD, Bingxi Sun , MIAO, Li Yan , DAI, Huixiong , BRAND, Adam , CHEN, Yongmei , PANDIT, Mandar B. , ZHOU, Qingjun
IPC分类号： H01L21/027 , H01L29/78 , H01L21/336
CPC分类号： H01L21/266 , H01L21/26586 , H01L21/31053 , H01L21/31122 , H01L21/31138 , H01L21/31144 , H01L21/823431 , H01L21/845 , H01L29/66803
摘要： Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate.
摘要翻译：本发明的实施例提供了一种用于图案化用于离子注入工艺的良好工艺控制的硬掩模层的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）。在一个实施例中，图案化设置在衬底上的硬掩模层的方法包括在设置在衬底上的硬掩模层上形成平坦化层，在平坦化层上设置图案化的光致抗蚀剂层，将平坦化层和硬掩模层图案化，在处理室中的图案化光致抗蚀剂层，暴露下面的衬底的第一部分，以及从衬底去除平坦化层。

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