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1. 发明申请

WO2005098929A3 METHOD OF FORMING SIDEWALL SPACERS 审中-公开
标题翻译：形成侧壁间隔件的方法
公开(公告)号：WO2005098929A3
公开(公告)日：2005-12-15
申请号：PCT/US2005010475
申请日：2005-03-29
申请人： ADVANCED MICRO DEVICES INC , LENSKI MARKUS , GRAETSCH FALK , REICHEL CARSTEN , SCHWAN CHRISTOPH , BIERSTEDT HELMUT , KAMMLER THORSTEN , MAZUR MARTIN
发明人： LENSKI MARKUS , GRAETSCH FALK , REICHEL CARSTEN , SCHWAN CHRISTOPH , BIERSTEDT HELMUT , KAMMLER THORSTEN , MAZUR MARTIN
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/28123 , H01L29/66492 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： The present invention allows the formation of sidewall spacers (217,218) adjacent a feature (206) on a substrate (201) without there being an undesirable erosion of the feature. The feature (206) is covered by one or more protective layers (220,207). A layer of a spacer material (211) is deposited over the feature (206) and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers (220, 207) are substantially not affected by the etchant. Thus, the one or more protective layers (220, 207) protect the feature from being exposed to the etchant.
摘要翻译：本发明允许在衬底（201）上形成与特征（206）相邻的侧壁间隔物（217,218），而不会对该特征造成不希望的腐蚀。特征（206）被一个或多个保护层（220,207）覆盖。在特征（206）上沉积一层间隔材料（211）并各向异性蚀刻。用于各向异性蚀刻的蚀刻剂适于选择性地去除间隔物材料，而一个或多个保护层（220,207）基本上不受蚀刻剂的影响。因此，一个或多个保护层（220,207）保护该特征免于暴露于蚀刻剂。

2. 发明申请

WO2006083546A3 IN SITU FORMED HALO REGION IN A TRANSISTOR DEVICE 审中-公开
标题翻译：在晶体管器件中形成的HALO区域
公开(公告)号：WO2006083546A3
公开(公告)日：2006-12-14
申请号：PCT/US2006001596
申请日：2006-01-17
申请人： ADVANCED MICRO DEVICES INC , KAMMLER THORSTEN , WEI ANDY , BIERSTEDT HELMUT
发明人： KAMMLER THORSTEN , WEI ANDY , BIERSTEDT HELMUT
IPC分类号： H01L21/336 , H01L21/265 , H01L29/10 , H01L29/165 , H01L29/78
CPC分类号： H01L21/26586 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： By performing a sequence of selective epitaxial growth processes with at least two different species, or by introducing a first dopant species prior to the epitaxial growth of a drain and source region, a halo region may be formed in a highly efficient manner, while at the same time the degree of lattice damage in the epitaxially grown semiconductor region is maintained at a low level. The method of forming a first semiconductor region (211) by a first epitaxial growth process, forming a second semiconductor region (210) by performing a second epitaxial growth process, whereas the first and second semiconductor regions compose different dopant species.
摘要翻译：通过用至少两种不同的物质执行选择性外延生长工艺的序列，或者通过在漏极和源极区域的外延生长之前引入第一掺杂剂物质，可以高效地形成卤素区域，而在同时，外延生长的半导体区域的晶格损伤程度保持在较低的水平。通过第一外延生长工艺形成第一半导体区域（211）的方法，通过执行第二外延生长工艺形成第二半导体区域（210），而第一和第二半导体区域构成不同的掺杂物质。

3. 发明申请

WO2005022608A2 SILICIDING SPACER IN INTEGRATED CIRCUIT TECHNOLOGY 审中-公开
标题翻译：集成电路技术中的硅化间隔器
公开(公告)号：WO2005022608A2
公开(公告)日：2005-03-10
申请号：PCT/US2004028282
申请日：2004-08-30
申请人： ADVANCED MICRO DEVICES INC , PATTON JEFFREY P , MAHANPOUR MEHRDAD , KAMMLER THORSTEN , BROWN DAVID E , BESSER PAUL R , CHAN SIMON SIU-SING , FRENKEL AUSTIN C
发明人： PATTON JEFFREY P , MAHANPOUR MEHRDAD , KAMMLER THORSTEN , BROWN DAVID E , BESSER PAUL R , CHAN SIMON SIU-SING , FRENKEL AUSTIN C
IPC分类号： H01L21/336 , H01L21/00
CPC分类号： H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method [900] of forming an integrated circuit [100] and a structure therefore is provided. A gate dielectric [104]is formed on a semiconductor substrate [102], and a gate [106] is formed over the gate dielectric [104]. Shallow source/drain junctions [304,306] are formed in the semiconductor substrate [102]. A sidewall spacer [402] is formed around the gate [106]. Deep source/drain junctions [504,506] are formed in the semiconductor substrate [102] using the sidewall spacer [402]. A siliciding spacer [610] is formed over the sidewall spacer [402] after forming the shallow and deep source/drain junctions [504,506]. A silicide [604] [606] is formed on the deep source/drain junctions [504,506] adjacent the siliciding spacer [610], and a dielectric layer [702] is deposited above the semiconductor substrate [102]. Contacts are then formed in the dielectric layer [702] to the silicide [604][606].
摘要翻译：提供了形成集成电路[100]的方法[900]和结构。在半导体衬底[102]上形成栅极电介质[104]，并且在栅极电介质[104]上形成栅极[106]。在半导体衬底[102]中形成浅的源极/漏极结[304,306]。围绕栅极[106]形成侧壁间隔件[402]。使用侧壁间隔物[402]在半导体衬底[102]中形成深的源极/漏极结[504,506]。在形成浅和深源极/漏极结[504,506]之后，在侧壁间隔物[402]上形成硅化隔离物[610]。在与硅化隔离物[610]相邻的深源极/漏极结[504,506]上形成硅化物[604] [606]，并且在半导体衬底[102]上方沉积介电层[702]。接着在介电层[702]中形成硅化物[604] [606]。

4. 发明申请

WO2008121326A3 AN SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO 审中-公开
标题翻译：具有减少长度的漏极和源极区域的SOI晶体管和受压介电材料相邻
公开(公告)号：WO2008121326A3
公开(公告)日：2008-12-18
申请号：PCT/US2008004065
申请日：2008-03-28
申请人： ADVANCED MICRO DEVICES INC , WEI ANDY , KAMMLER THORSTEN , BOSCHKE ROMAN , SCOTT CASEY
发明人： WEI ANDY , KAMMLER THORSTEN , BOSCHKE ROMAN , SCOTT CASEY
IPC分类号： H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/6659 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： By reconfiguring material (202, 302, 402) in a recess (210R, 310R, 410R) formed in drain and source regions (251, 351, 451) of SOI transistors (250, 350, 450), the depth of the recess (210R, 310R, 410R) may be increased down to the buried insulating layer (205, 305, 405) prior to forming respective metal suicide regions (254), thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element (250, 350, 450) is covered by a highly stressed dielectric material (203). The material redistribution may be accomplished on the basis of a high temperature hydrogen bake (211, 311) or an isotropic etch.
摘要翻译：通过在形成在SOI晶体管（250,350,450）的漏极和源极区域（251,351,451）中的凹部（210R，310R，410R）中重新配置材料（202,302,402），凹部 210R，310R，410R）可以在形成相应的金属硅化物区域（254）之前向下增加到掩埋绝缘层（205,305,405），从而当对应的晶体管元件（250， 350,450）被高应力介电材料（203）覆盖。材料再分配可以基于高温氢气烘烤（211,311）或各向同性蚀刻来实现。

5. 发明申请

WO2007027473A2 TECHNIQUE FOR FORMING RECESSED STRAINED DRAIN/SOURCE IN NMOS AND PMOS TRANSISTORS 审中-公开
标题翻译：在NMOS和PMOS晶体管中形成受压应变的漏极/源极的技术
公开(公告)号：WO2007027473A2
公开(公告)日：2007-03-08
申请号：PCT/US2006032743
申请日：2006-08-23
申请人： ADVANCED MICRO DEVICES INC , HOENTSCHEL JAN , WEI ANDY , KAMMLER THORSTEN , RAAB MICHAEL
发明人： HOENTSCHEL JAN , WEI ANDY , KAMMLER THORSTEN , RAAB MICHAEL
IPC分类号： H01L21/8238 , H01L21/265 , H01L27/092
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/1203 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： By forming a strained semiconductor layer (117, 217) in a PMOS transistor (110, 210), a corresponding compressively strained channel region (11 IA) may be achieved, while, on the other hand, a corresponding strain in the NMOS transistor (120, 220) may be relaxed. Due to the reduced junction resistance caused by the reduced band gap of silicon/germanium in the NMOS transistor (120, 220), an overall performance gain is accomplished, wherein, particularly in partially depleted SOI devices, the deleterious floating body effect is also reduced, due to the increased leakage currents generated by the silicon/germanium layer (117, 127, 217, 227) in the PMOS (110, 210) and NMOS transistor (120, 220).
摘要翻译：通过在PMOS晶体管（110,210）中形成应变半导体层（117,217），可以实现对应的压缩应变通道区域（11A），而另一方面可以实现NMOS晶体管 120,220）可以放松。由于由NMOS晶体管（120,220）中硅/锗的带隙减小引起的结电阻降低，所以实现了整体性能增益，其中特别是在部分耗尽的SOI器件中，有害的浮体效应也降低，由于PMOS（110,210）和NMOS晶体管（120,220）中的硅/锗层（117,127,217,227）产生的增加的漏电流。

6. 发明申请

WO2008094653A3 METHOD FOR FORMING SILICON/GERMANIUM CONTAINING DRAIN/SOURCE REGIONS IN TRANSISTORS WITH REDUCED SILICON/GERMANIUM LOSS 审中-公开
标题翻译：在具有降低的硅/锗损失的晶体管中形成含有硅/锗含量/源区的方法
公开(公告)号：WO2008094653A3
公开(公告)日：2008-09-12
申请号：PCT/US2008001292
申请日：2008-01-31
申请人： ADVANCED MICRO DEVICES INC , GEHRING ANDREAS , WIATR MACIEJ , WEI ANDY , KAMMLER THORSTEN , SCOTT CASEY , BOSCHKE ROMAN
发明人： GEHRING ANDREAS , WIATR MACIEJ , WEI ANDY , KAMMLER THORSTEN , SCOTT CASEY , BOSCHKE ROMAN
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/1087 , H01L29/165 , H01L29/6653 , H01L29/66636
摘要： By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal suicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.
摘要翻译：通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

7. 发明申请

WO2004023533A2 SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：WO2004023533A2
公开(公告)日：2004-03-18
申请号：PCT/US0327366
申请日：2003-08-29
申请人： ADVANCED MICRO DEVICES INC
发明人： LUNING SCOTT , WIECZOREK KARSTEN , KAMMLER THORSTEN
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78 , H01L21/00
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).
摘要翻译：一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。栅极结构（112）形成在半导体衬底（102）的主表面（104）上。在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。源极（132）和漏极（134）区域形成在半导体衬底（102）中。在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。

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