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1. 发明申请

WO2003003451A1 ISOLATION OF SONOS DEVICES 审中-公开
标题翻译： SONOS设备的隔离
公开(公告)号：WO2003003451A1
公开(公告)日：2003-01-09
申请号：PCT/US2001/049047
申请日：2001-12-14
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED
发明人： YANG, Jean, Yee-Mei , RAMSBEY, Mark, T. , LINGUNIS, Emmanuil, Manos , WU, Yider , KAMAL, Tazrien , HE, Yi , HSIA, Edward , SHIRAIWA, Hidehiko
IPC分类号： H01L21/8246
CPC分类号： H01L21/2652 , H01L21/2658 , H01L27/11568 , H01L29/66833
摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
摘要翻译：本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷捕获电介质的第三层（如果存在）在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷捕获电介质的第三层（如果存在）以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或在电荷俘获电介质的第三层上形成附加材料。

2. 发明申请

WO2005078791A1 POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL 审中-公开
标题翻译：用于补充位冲突改进和SONOS存储单元充电改进的POCKET IMPLAN
公开(公告)号：WO2005078791A1
公开(公告)日：2005-08-25
申请号：PCT/US2004/042855
申请日：2004-12-17
申请人： ADVANCED MICRO DEVICES, INC. , LINGUNIS, Emmanuil, H. , WONG, Nga-Ching, Alan , HADDAD, Sameer , RANDOLPH, Mark, W. , RAMSBEY, Mark, T. , MELIK-MARTIROSIAN, Ashot , RUNNION, Edward, F. , HE, Yi
发明人： LINGUNIS, Emmanuil, H. , WONG, Nga-Ching, Alan , HADDAD, Sameer , RANDOLPH, Mark, W. , RAMSBEY, Mark, T. , MELIK-MARTIROSIAN, Ashot , RUNNION, Edward, F. , HE, Yi
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层（608）的一部分形成在衬底（602）上，并且在电荷俘获电介质层（608）的部分上形成抗蚀剂（614）。对抗蚀剂（614）进行图案化，并且以一定角度执行凹穴注入（630）以在衬底（602）内建立凹穴注入（620）。然后执行位线植入（634）以在衬底（602）内建立掩埋位线（640）。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层（608）。字线材料（660）形成在电荷俘获电介质层的剩余部分上并被图案化以形成覆盖在位线（640）上的字线（662）。口袋植入物（620）用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

3. 发明申请

WO2004051753A1 SILICON NITRADE CHARGE TRAPPING MEMORY DEVICE 审中-公开
标题翻译：硅镍电池捕捉存储器件
公开(公告)号：WO2004051753A1
公开(公告)日：2004-06-17
申请号：PCT/US2003/021676
申请日：2003-07-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： RANDOLPH, Mark, W. , CHANG, Chi , HE, Yi , ZHENG, Wei , RUNNION, Edward, F.
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/14 , H01L29/7923
摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well (510) is formed in a semiconductor substrate (529). A plurality of N-type impurity concentrations (550, 555) are formed in the isolated P-well (510) and a nitride memory cell (560) is fabricated between two of the N-type impurity concentrations (550, 555). Finally, an electrical contact (590) is coupled to the isolated P-well (510).
摘要翻译：本发明是一种擦除氮化物存储器件的方法和系统。在本发明的一个实施例中，在半导体衬底（529）中形成隔离的P阱（510）。在隔离的P阱（510）中形成多个N型杂质浓度（550,555），并且在两种N型杂质浓度（550,555）之间制造氮化物存储单元（560）。最后，电触点（590）耦合到隔离的P阱（510）。

4. 发明申请

WO2004051667A1 IMPROVED SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：用于编程非易失性存储单元的改进系统
公开(公告)号：WO2004051667A1
公开(公告)日：2004-06-17
申请号：PCT/US2003/023085
申请日：2003-07-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： HE, Yi , LIU, Zhizheng , RANDOLPH, Mark, W. , HADDAD, Sameer, S.
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491
摘要： An array (40) of dual bit dielectric memory cells (48) comprises a plurality of bit lines. A first bit line (201) forms a source region for each of a plurality of memory cells (38) within a column of memory cells within the array (40). A second bit line (202) forms a drain region for each of the plurality of memory cells (38) within the column. A channel region (50) of the opposite conductivity is positioned between the first bit line (201) and the second bit line (202) and forms a junction with each. A selected word line (211) is positioned over the channel region (50) and forms a gate (60) over each for a plurality of memory cells (48) within a same row. A plurality of non-selected word lines (210, 212), are each parallel to the selected word line (211) and each form a gate (60) over one of the plurality of memory cells (48) within the column other than the selected one of the plurality of memory cells (49). A word line control circuit (46) applies a positive programming voltage (220) to the selected word line (211) while a bit line control circuit (44) simultaneously applies a positive drain voltage to the drain bit line (202) and a positive source voltage to the source bit line (201), the positive source voltage being less than the positive drain voltage.
摘要翻译：双位介质存储器单元（48）的阵列（40）包括多个位线。第一位线（201）为阵列（40）内的存储单元列内的多个存储器单元（38）中的每一个形成源区域。第二位线（202）为列内的多个存储单元（38）中的每一个形成漏极区。具有相反电导率的沟道区域（50）位于第一位线（201）和第二位线（202）之间，并且与第一位线形成结。所选择的字线（211）位于信道区域（50）上方，并在同一行内的多个存储单元（48）上形成一个门（60）。多个未选择的字线（210,212）各自平行于所选择的字线（211），并且每个在所述列内的多个存储器单元（48）中的一个上形成门（60），而不是所选择的多个存储单元（49）中的一个。字线控制电路（46）将正编程电压（220）施加到所选择的字线（211），同时位线控制电路（44）同时向漏位线（202）施加正漏电压，源极电压（201），正电源电压小于正漏极电压。

5. 发明申请

WO2004051663A1 IMPROVED PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：用于读取非易失性存储器单元的改进的预充电方法
公开(公告)号：WO2004051663A1
公开(公告)日：2004-06-17
申请号：PCT/US2003/023087
申请日：2003-07-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： HE, Yi , LIU, Zhizheng , RANDOLPH, Mark, W. , RUNNION, Edward, F. , HAMILTON, Darlene , CHEN, Patu-Ling , LE, Binh, Q.
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C16/0475 , G11C16/24
摘要： A method of detecting a charge stored on a charge storage region (62) of a first dual bit dielectric memory cell (49) within an array (40) of dual bit dielectric memory cells (48) comprises coupling a first bit line (201) that forms a source junction with a channel region (50) of the first memory cell (49) to ground (68). A high voltage is applied to a gate (60) of the first memory cell (49) and to a second bit line (202) that is the next bit line to the right of the first bit line (201) and separated from the first bit line (201) only by the channel region (50). A third bit line (203), that is the next bit line to the right of the second bit line (202), is isolated such that its potential is effected only by its junctions with the a second channel region (50) and a third channel region (50) on opposing sides of the third bit line (203). A high voltage is applied to a pre-charge bit line that is to the right of the third bit line (203) and current flow is detected at the second bit line (202) to determine the programmed status of a source bit (62) of the first memory cell (49).
摘要翻译：检测存储在双位介质存储单元（48）的阵列（40）内的第一双位介质存储单元（49）的电荷存储区域（62）上的电荷的方法包括将第一位线（201）其形成与第一存储单元（49）的沟道区（50）到地（68）的源极结。向第一存储单元（49）的栅极（60）和第二位线（202）施加高电压，第二位线（202）是第一位线（201）右侧的下一个位线，并且与第一位线位线（201）仅通过通道区域（50）。作为第二位线（202）右侧的下一个位线的第三位线（203）是隔离的，使得其电位仅通过其与第二通道区域（50）的连接和第三位线在第三位线（203）的相对侧上的通道区域（50）。高电压被施加到位于第三位线（203）右侧的预充电位线，并且在第二位线（202）处检测电流以确定源位（62）的编程状态，的第一存储单元（49）。

6. 发明申请

WO2004070727A2 IMPROVED METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取非易失性存储单元阵列的非易失性存储器单元的非易失性存储单元阵列的改进方法
公开(公告)号：WO2004070727A2
公开(公告)日：2004-08-19
申请号：PCT/US2004/000495
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , HSIA, Edward , HAMILTON, Darlene, G. , SHIEH, Ming-Huei , RUNNION, Edward , AJIMINE, Eric , CHEN, Pau-Ling , RANDOLPH, Mark, W. , HE, Yi
发明人： HSIA, Edward , HAMILTON, Darlene, G. , SHIEH, Ming-Huei , RUNNION, Edward , AJIMINE, Eric , CHEN, Pau-Ling , RANDOLPH, Mark, W. , HE, Yi
IPC分类号： G11C
CPC分类号： G11C29/82 , G11C16/0491 , G11C16/3404
摘要： A method of storing a data pattern and reproducing the data pattern within an array 30 of memory cells 48, which includes active columns 45b and 45g and inactive columns 46c and 45f, comprises storing the data pattern within the active columns 45b and 45g. An inactive memory cell programming pattern 32 is identified. The inactive memory cell programming pattern 32 identifies all, or a selected plurality, of the memory cells 48 in the inactive columns 45c and 45f in which a charge is to be stored for the purpose of periodically storing a charge in such memory cells 48 to prevent over erasure, during bulk erase, and leakage to active memory cells 48.
摘要翻译：存储数据模式并将数据模式再现到包括有效列45b和45g以及非活动列46c和45f的存储单元48的阵列30内的方法包括将数据模式存储在活动列45b和45g内。识别非活动存储器单元编程模式32。非活动存储器单元编程模式32识别无效列45c和45f中的所有存储器单元48或所选择的多个存储器单元48，其中为了周期性地将电荷存储在这样的存储器单元48中以防止过度擦除，在批量擦除期间，并泄漏到有源存储器单元48。

7. 发明申请

WO2005038815A1 MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL 审中-公开
标题翻译：存储器件和使用正栅极应力来恢复过度电池的方法
公开(公告)号：WO2005038815A1
公开(公告)日：2005-04-28
申请号：PCT/US2004/030694
申请日：2004-09-16
申请人： ADVANCED MICRO DEVICES, INC. , HAMILTON, Darlene , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi , HSIA, Edward , TANPAIROJ, Kulachet , LEE, Mimi , MADHANI, Alykhan
发明人： HAMILTON, Darlene , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi , HSIA, Edward , TANPAIROJ, Kulachet , LEE, Mimi , MADHANI, Alykhan
IPC分类号： G11C16/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells (10) includes pre-programming (100) the plurality of memory cells (10), applying an erase pulse (110) to the plurality of memory cells (10) followed by an erase verification (120). The erase verification (120) is followed by soft programming (135) any memory cells having a threshold voltage below a predetermined minimum level (V TMIN ) and applying a positive gate stress (130) to the plurality of memory cells (10). The erase method prevents overerasing and provides a tightened threshold voltage distribution.
摘要翻译：擦除由多个存储单元（10）组成的闪存电可擦除只读存储器（EEPROM）器件的方法包括：对所述多个存储器单元（10）进行预编程（100），向所述多个存储器单元（10）施加擦除脉冲（110）多个存储器单元（10），随后进行擦除验证（120）。擦除验证（120）之后是具有低于预定最小电平（VTMIN）的阈值电压并向多个存储单元（10）施加正门应力（130）的任何存储器单元（135）进行软编程（135）。擦除方法可以防止过压，并提供紧固的阈值电压分布。

8. 发明申请

WO2003100790A1 METHOD OF ERASING A FLASHING MEMORY USING A PRE-ERASING STEP 审中-公开
标题翻译：使用预擦除步骤擦除闪存的方法
公开(公告)号：WO2003100790A1
公开(公告)日：2003-12-04
申请号：PCT/US2003/012636
申请日：2003-04-22
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LE, Binh, Quang , HAMILTON, Darlene , TANPAIROJ, Kulachet , LIU, Zhizheng , HE, Yi , ZHENG, Wei , CHEN, Pau-Ling , VANBUSKIRK, Michael
IPC分类号： G11C16/16
CPC分类号： G11C16/107 , G11C11/5635 , G11C11/5671 , G11C16/0475 , G11C16/16
摘要： A method of erasing a sector of flash memory cells wherein a first set of preset pre-erase voltages is applied to the sector of flash memory cells (402). After the first set of preset pre-erase voltages is applied it is determined if another set of preset pre-erase voltages is to be applied to the sector of flash memory cells (410). If another set of preset pre-erase voltages is not to be applied, a standard erase routine is applied to the sector (411).
摘要翻译：一种擦除闪存单元扇区的方法，其中第一组预置预擦除电压被施加到快闪存储单元（402）的扇区。在施加了第一组预设预擦除电压之后，确定是否将另外一组预设预擦除电压施加到闪存单元（410）的扇区。如果不应用另一组预设预擦除电压，则对扇区（411）应用标准擦除例程。

9. 发明申请

WO2003079370A1 OVERERASE CORRECTION METHOD 审中-公开
标题翻译：过度校正方法
公开(公告)号：WO2003079370A1
公开(公告)日：2003-09-25
申请号：PCT/US2003/004606
申请日：2003-02-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LIU, Zhizheng , HE, Yi , RANDOLPH, Mark, W.
IPC分类号： G11C16/34
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/0491 , G11C16/3404 , G11C16/344
摘要： A method of overerase correction of a multi-bit memory cell by applying (424) a soft programming pulse having a ratio of Vg/Vd≥2 to overease bits.
摘要翻译：通过将（424）具有Vg / Vd> = 2的比率的软编程脉冲应用于过度比特来对多比特存储器单元进行过度修正的方法。

10. 发明申请

WO2004049453A1 RETROGRADE CHANNEL DOPING TO IMPROVE SHORT CHANNEL EFFECT 审中-公开
标题翻译：改进通道，改善短路通道效果
公开(公告)号：WO2004049453A1
公开(公告)日：2004-06-10
申请号：PCT/US2003/021682
申请日：2003-07-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ZHENG, Wei , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L29/105 , H01L29/7881 , H01L29/792
摘要： A memory semiconductor cell (30) comprises a gate region (16), a source region (14) and a drain region (14). A channel region (17) is formed between the source region (14) and the drain region (14). The channel region (17) comprises a first channel portion (33) with a first concentration of doping material, the first channel portion (33) disposed adjacent to an edge of the channel region (17) closest to and substantially parallel to the gate region (16). The channel region (17) further comprises a second channel portion (31) with a second concentration of doping material, the second channel portion (31) disposed substantially parallel to the first channel portion (33) and a third channel portion (32), disposed between the first channel portion (33) and the second channel portion (31), with a third concentration of doping material. The third concentration is lower than the first concentration and lower than the second concentration. The memory cell may be one of two general types of non-volatile memory, a floating gate cell or a nitride read only memory (NROM), whereby layer (12B) in a floating gate or a nitride layer respectively.
摘要翻译：存储器半导体单元（30）包括栅极区（16），源极区（14）和漏极区（14）。在源极区域（14）和漏极区域（14）之间形成沟道区域（17）。沟道区域（17）包括具有第一浓度掺杂材料的第一沟道部分（33），第一沟道部分（33）邻近沟道区域（17）的与栅极区域最接近且基本平行的边缘（16）。通道区域（17）还包括具有第二浓度掺杂材料的第二通道部分（31），第二通道部分（31）基本上平行于第一通道部分（33）和第三通道部分（32）设置，设置在第一通道部分（33）和第二通道部分（31）之间，具有第三浓度的掺杂材料。第三浓度低于第一浓度，低于第二浓度。存储单元可以是两种一般类型的非易失性存储器，浮动栅极单元或氮化物只读存储器（NROM）中的一种，其中分别在浮动栅极或氮化物层中的层（12B）。

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