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1. 发明申请

WO2005020323A2 FIELD EFFECT TRANSISTOR HAVING INCREASED CARRIER MOBILITY 审中-公开
标题翻译：具有增加载波移动性的场效应晶体管
公开(公告)号：WO2005020323A2
公开(公告)日：2005-03-03
申请号：PCT/US2004/025565
申请日：2004-08-05
申请人： ADVANCED MICRO DEVICES, INC. , ANG, Boon-Yong , XIANG, Qi , GOO, Jung-Suk
发明人： XIANG, Qi , GOO, Jung-Suk
IPC分类号： H01L27/00
CPC分类号： H01L29/4983 , H01L29/02 , H01L29/4925 , H01L29/513 , H01L29/78 , H01L29/7845 , Y10S438/938
摘要： According to one exemplary embodiment, a FET which is situated over a substrate (104), comprises a channel (112) situated in the substrate (104). The FET further comprises a first gate dielectric (116) situated over the channel (112), where the first gate dielectric (116) has a first coefficient of thermal expansion. The FET further comprises a first gate electrode (114) situated over the first gate dielectric (116), where the first gate electrode (114) has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel (112).
摘要翻译：根据一个示例性实施例，位于衬底（104）上方的FET包括位于衬底（104）中的通道（112）。 FET还包括位于通道（112）上方的第一栅极电介质（116），其中第一栅极电介质（116）具有第一热膨胀系数。 FET还包括位于第一栅极电介质（116）上方的第一栅电极（114），其中第一栅电极（114）具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一栅电极热膨胀系数，从而导致FET中载流子迁移率的增加。例如，第二热膨胀系数可以大于第一热膨胀系数。载流子迁移率的增加可以由例如在通道（112）中产生的拉伸应变引起。

2. 发明申请

WO2005048333A1 METHOD FOR INTEGRATING A HIGH-K GATE DIELECTRIC IN A TRANSISTOR FABRICATION PROCESS 审中-公开
标题翻译：用于在晶体管制造工艺中集成高K栅介质的方法
公开(公告)号：WO2005048333A1
公开(公告)日：2005-05-26
申请号：PCT/US2004/033411
申请日：2004-10-08
申请人： ADVANCED MICRO DEVICES, INC. , LABELLE, Catherine, B. , ANG, Boon-Yong , JEON, Joong, S. , HOLBROOK, Allison, Kay , XIANG, Qi , ZHONG, Huicai
发明人： LABELLE, Catherine, B. , ANG, Boon-Yong , JEON, Joong, S. , HOLBROOK, Allison, Kay , XIANG, Qi , ZHONG, Huicai
IPC分类号： H01L21/28
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28247 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate (104), where the substrate (104) includes a high-k dielectric layer situated over the substrate (104) and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching (202) the gate electrode layer and the high-k dielectric layer to form a gate stack (102), where the gate stack (102) comprises a high-k dielectric segment (106) situated over the substrate (104) and a gate electrode segment (108) situated over the high-k dielectric segment (106). According to this exemplary embodiment, the method further comprises performing (204) a nitridation process on the gate stack (102). The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls (110) of the gate stack (102), where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment (106) and form an oxygen diffusion barrier in the high-k dielectric segment (106), for example.
摘要翻译：根据一个示例性实施例，一种用于在衬底（104）上形成场效应晶体管的方法，其中衬底（104）包括位于衬底（104）上方的高k电介质层和位于衬底高k电介质层包括蚀刻（202）栅电极层和高k电介质层以形成栅极堆叠（102）的步骤，其中栅极堆叠（102）包括高k介电段（106））和位于所述高k电介质段（106）之上的栅电极段（108）。根据该示例性实施例，该方法还包括在栅极堆叠（102）上执行（204）氮化处理。氮化工艺可以通过例如利用等离子体来氮化栅叠层（102）的侧壁（110）来进行，其中等离子体包括氮。例如，氮化处理可以使氮进入高k电介质段（106）并在高k电介质段（106）中形成氧扩散阻挡层。

3. 发明申请

WO2005048320A3 METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FORM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 审中-公开
公开(公告)号：WO2005048320A3
公开(公告)日：2005-05-26
申请号：PCT/US2004/028486
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , ZHONG, Huicai , GOO, Jung-Suk , HOLBROOK, Allison, Kay , JEON, Joong, S. , KLUTH, George, Jonathan
发明人： XIANG, Qi , ZHONG, Huicai , GOO, Jung-Suk , HOLBROOK, Allison, Kay , JEON, Joong, S. , KLUTH, George, Jonathan
IPC分类号： H01L21/8238
摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).

4. 发明申请

WO2005071738A2 SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE 审中-公开
标题翻译： SHOWOW TRENCH隔离过程和结构
公开(公告)号：WO2005071738A2
公开(公告)日：2005-08-04
申请号：PCT/US2004/043107
申请日：2004-12-21
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
发明人： XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
IPC分类号： H01L21/762
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material (36) is formed after the trench (34) is formed. The process can be utilized on a compound semiconductor layer (15) above a buried oxide (Box) layer (14).
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。在形成沟槽（34）之后形成应变材料（36）。该方法可以用在掩埋氧化物（Box）层（14）上方的化合物半导体层（15）上。

5. 发明申请

WO2005071728A1 METHOD OF FABRICATING A STRAINED FINFET CHANNEL 审中-公开
标题翻译：制造应变FINFET通道的方法
公开(公告)号：WO2005071728A1
公开(公告)日：2005-08-04
申请号：PCT/US2004/043106
申请日：2004-12-21
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
发明人： XIANG, Qi , PAN, James, N. , GOO, Jung-Suk
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842
摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer (140) above an insulating layer (130), providing a trench (142) in the compound semiconductor layer (140), and providing a strained semiconductor layer (144) above the compound semiconductor layer (140) and within the trench (142). The method can also include removing the strained semiconductor layer (144) from above the compound semiconductor layer (140), thereby leaving the strained semiconductor layer (144) within the trench (142) and removing the compound semiconductor layer (140) to leave the strained semiconductor layer (144) and form the fin-shaped channel region (152).
摘要翻译：示例性实施例涉及FinFET沟道结构形成的方法。该方法可以包括在绝缘层（130）之上提供化合物半导体层（140），在化合物半导体层（140）中提供沟槽（142），并且在化合物半导体层上方提供应变半导体层（144） 140）并且在沟槽（142）内。该方法还可以包括从化合物半导体层（140）上方去除应变半导体层（144），从而将应变半导体层（144）留在沟槽（142）内，并去除化合物半导体层（140）以离开应变半导体层（144）并形成鳍状沟道区域（152）。

6. 发明申请

WO2005101521A1 SEMICONDUCTOR ON INSULATOR SUBSTRATE AND DEVICES FORMED THEREFROM 审中-公开
标题翻译：绝缘体基板上的半导体及其形成的器件
公开(公告)号：WO2005101521A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/010574
申请日：2005-03-28
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi
发明人： XIANG, Qi
IPC分类号： H01L29/786
CPC分类号： H01L29/78603 , H01L29/7842 , H01L29/78684
摘要： A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material (52) having a perovskite lattice, such as a rare earth scandate. The dielectric material (52) is selected to have an effective lattice constant that enables growth of semiconductor material (54) having a diamond lattice directly on the dielectric (52). Examples of the rare earth scandate dielectric include gadolinium scandate (GdScO 3 ), dysprosium scandate (DyScO 3 ), and alloys of gadolinium and dysprosium scandate (Gd 1-X Dy X Sc0 3 ).
摘要翻译：绝缘体上半导体（SOI）器件由具有钙钛矿晶格的介电材料（52）的层构成，例如稀土钪酸盐。电介质材料（52）被选择为具有有效晶格常数，使得能够在电介质（52）上直接形成具有金刚石晶格的半导体材料（54）的生长。稀土钪酸盐电介质的实例包括钪钪（GdScO 3），镝镝（DyScO3）以及钆和镝镝合金（Gd1-XDyXSc03）。

7. 发明申请

WO2003036701A1 LOW-TEMPERATURE POST-DOPANT ACTIVATION PROCESS 审中-公开
标题翻译：低温后激活过程
公开(公告)号：WO2003036701A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/032555
申请日：2002-10-11
申请人： ADVANCED MICRO DEVICES, INC. , YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
发明人： YU, Bin , OGLE, Robert, B. , PATON, Eric, N. , TABERY, Cyrus, E. , XIANG, Qi
IPC分类号： H01L21/268
CPC分类号： H01L29/665 , H01L21/268
摘要： A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode (24) over a substrate (10) and a gate oxide (16) between the gate electrode (24) and the substrate (10); forming source/drain extensions (30, 32) in the substrate (10); forming first and second sidewall spacers (36, 38); implanting dopants (44) within the substrate (10) to form source/drain regions (40, 42) in the substrate (10) adjacent to the sidewalls spacers (36, 38); laser thermal annealing to activate the source/drain regions (40, 42); depositing a layer of nickel (46) over the source/drain regions (40, 42); and annealing to form a nickel silicide layer (46) disposed on the source/drain regions (40, 42). The source/drain extensions (30, 32) and sidewall spacers (36, 38) are adjacent to the gate electrode (24). The source/drain extensions (30, 32) can have a depth of about 5 to 30 nanometers, and the source/drain regions (40, 42) can have a depth of about 40 to 100 nanometers. The annealing is at temperatures from about 350 to 500 °C.
摘要翻译：一种制造MOSFET半导体器件的方法包括在栅电极（24）和衬底（10）之间的衬底（10）和栅氧化层（16）上形成栅电极（24）。在所述衬底（10）中形成源极/漏极延伸部（30,32）; 形成第一和第二侧壁间隔件（36,38）; 在所述衬底（10）内注入掺杂剂（44）以在所述衬底（10）中邻近所述侧壁间隔物（36,38）形成源/漏区（40,42）; 激光热退火以激活源/漏区（40,42）; 在源/漏区（40,42）上沉积一层镍（46）; 和退火以形成设置在源/漏区（40,42）上的硅化镍层（46）。源极/漏极延伸部（30,32）和侧壁间隔物（36,38）与栅电极（24）相邻。源极/漏极扩展部（30,32）可以具有约5至30纳米的深度，并且源极/漏极区域（40,42）可以具有约40至100纳米的深度。退火温度在约350-500℃

8. 发明申请

WO2003032400A1 SEMICONDUCTOR DEVICE FORMED WITH DISPOSABLE SPACER AND LINER USING HIGH-K MATERIAL AND METHOD OF FABRICATION 审中-公开
标题翻译：使用高K材料和制造方法形成具有可分散间隔物和衬里的半导体器件
公开(公告)号：WO2003032400A1
公开(公告)日：2003-04-17
申请号：PCT/US2002/030840
申请日：2002-09-26
申请人： ADVANCED MICRO DEVICES, INC. , YU, Bin , XIANG, Qi , WANG, HaiHong
发明人： YU, Bin , XIANG, Qi , WANG, HaiHong
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/6653 , H01L29/6659
摘要： A semiconductor device (10) and method of manufacture. A liner (62) composed of a high-K material having a relative permittivity of greater than eight is formed adjacent at least the sidewalls of a gate (28). Sidewall spacers (66) are formed adjacent the gate and spaced apart from the gate by the liner. The liner can be removed using an etch process that has substantially no reaction with a gate dielectric (34) of the gate.
摘要翻译：一种半导体器件（10）及其制造方法。由栅极（28）的至少侧壁形成由相对介电常数大于8的高K材料构成的衬垫（62）。侧壁间隔件（66）邻近闸门形成并且通过衬套与闸门间隔开。可以使用基本上不与栅极的栅极电介质（34）反应的蚀刻工艺来去除衬里。

9. 发明申请

WO2006052379A1 STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：绝缘子半导体器件上的全绝缘硅及其制造方法
公开(公告)号：WO2006052379A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/036894
申请日：2005-10-12
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi , SUBBA, Niraj , MASZARA, Witold, P. , KRIVOKAPIC, Zoran , LIN, Ming-Ren
发明人： XIANG, Qi , SUBBA, Niraj , MASZARA, Witold, P. , KRIVOKAPIC, Zoran , LIN, Ming-Ren
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate (102) is provided having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104). A deep trench isolation (108) is formed, introducing strain to the semiconductor layer (106). A gate dielectric (202) and a gate (204) are formed on the semiconductor layer (106). A spacer (304) is formed around the gate (204), and the semiconductor layer (106) and the insulator (104) are removed outside the spacer (304). Recessed source/drain (402) are formed outside the spacer (304).
摘要翻译：提供了一种半导体衬底（102），其上具有绝缘体（104），绝缘体（104）上具有半导体层（106）。形成深沟槽隔离（108），将应变引入半导体层（106）。在半导体层（106）上形成栅极电介质（202）和栅极（204）。在栅极（204）周围形成间隔物（304），并且将半导体层（106）和绝缘体（104）去除在间隔物304的外部。嵌入式源极/漏极（402）形成在间隔物（304）的外侧。

10. 发明申请

WO2005064644A2 STRAINED SILICON MOSFETS HAVING REDUCED DIFFUSION OF N-TYPE DOPANTS 审中-公开
标题翻译：应变N型多晶硅扩散减少的硅MOSFET
公开(公告)号：WO2005064644A2
公开(公告)日：2005-07-14
申请号：PCT/US2004/028593
申请日：2004-09-01
申请人： ADVANCED MICRO DEVICES, INC. , XIANG, Qi
发明人： XIANG, Qi
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/268 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/785
摘要： Processing is performed during fabrication of a strained silicon NMOS device to create point defects in silicon germanium (40) portions of source regions, and optionally of drain regions, prior to activation of source and drain region dopants. The point defects retard diffusion of the n-type dopants in the silicon germanium material (40), effectively lengthening the duration of the diffusivity transient region and resulting in lower overall dopant diffusivity during activation.
摘要翻译：在制造应变硅NMOS器件期间执行处理，以在激活源极和漏极区掺杂剂之前在源极区和任选的漏极区的硅锗（40）部分中产生点缺陷。点缺陷阻碍了硅锗材料（40）中n型掺杂剂的扩散，有效地延长了扩散瞬态区的持续时间，并导致活化期间整体掺杂剂扩散率降低。

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